Commit graph

73706 commits

Author SHA1 Message Date
Bin Meng
478f7fc6a0 nvme: Skip block device creation for inactive namespaces
At present for each namespace there is a block device created for it.
There is no issue if the number of supported namespaces reported from
the NVMe device is only 1.

Since QEMU commit 7f0f1acedf15 ("hw/block/nvme: support multiple namespaces"),
the number of supported namespaces reported has been changed from 1
to 256, but not all of them are active namespaces. The actual active
one depends on the QEMU command line parameters. A common case is
that namespace 1 being active and all other 255 being inactive.

If a namespace is inactive, the namespace identify command returns a
zero filled data structure. We can use field NSZE (namespace size) to
decide whether a block device should be created for it.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-06-23 17:21:14 +08:00
Bin Meng
84344258f2 nvme: Move block dev creation from uclass post_probe() to driver probe()
At present the block device creation happens in the NVMe uclass
driver post_probe() phase. In preparation to support multiple
namespaces, we should issue namespace identify before creating
block devices but that touches the underlying hardware hence it
is not appropriate to do such in the uclass driver post_probe().
Let's move it to driver probe() phase instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-06-23 17:21:14 +08:00
Wesley Sheng
c3e52c71bb nvme: Remove the redundant aqa value setting
AQA (Admin Queue Attributes) register is a dword size with
lower word of ASQS, and higher word of ACQS.

The code set the variable aqa twice, but it is redundant.

Signed-off-by: Wesley Sheng <wesleyshenggit@sina.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-06-23 17:21:14 +08:00
Wesley Sheng
859b33c948 nvme: Correct the prps per page calculation method
Each prp is 8 bytes, calculate the number of prps
per page should just divide page size by 8
there is no need to minus 1

Signed-off-by: Wesley Sheng <wesleyshenggit@sina.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-06-23 17:21:14 +08:00
David Lamparter
b12f62374e nvme: fix for big endian systems
writel() and co. already include the endian swap;  doing the swap twice
is, er, unhelpful.

Tested on a P4080DS, which boots perfectly fine off NVMe with this.

Signed-off-by: David Lamparter <equinox@diac24.net>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-06-23 17:21:14 +08:00
Bin Meng
6fbe06a6ce x86: Discard .note.gnu.property sections
When switching to kernel.org x86_64 gcc 11.1.0 toolchain, u-boot.rom
built from qemu-x86_defconfig no longer boots anymore. Investigation
shows that U-Boot fails at a very early stage during the boot process,
in fdtdec_prepare_fdt() where fdt_check_header() complains that there
is not a valid device tree found at gd->fdt_blob which points to _end.
Now _end points to an allocated section .note.gnu.property which of
course is wrong.

This issue is however not seen when using the default Ubuntu 20.04 gnu
toolchain (gcc 9.3.0 with binutils 2.34). Further investigation shows
that it is caused by a behavior change of binutils v2.36 which is part
of the kernel.org gcc 11.1.0 toolchain, via the following commit:

  939b95c77bf2 ("Linux/x86: Configure gas with --enable-x86-used-note by default")

In fact, there was already a regression bug report [1] for binutils two
months ago, but the binutils folks did not think it is a bug :(

To resolve this, there are several options:

* pass -Wa,-mx86-used-note=no to gas
* pass -R .note.gnu.property to objcopy
* discard the section in the linker script

Linux kernel uses the discard way [2], so let's do the same for U-Boot.

[1] https://sourceware.org/bugzilla/show_bug.cgi?id=27753
[2] commit 4caffe6a28d3 ("x86/vdso: Discard .note.gnu.property sections in vDSO")

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-06-23 17:21:14 +08:00
Michal Simek
be2d1a87c7 spl: fit: Also record architecture in /fit-images
On ARM64 secure OS can run as 64bit or 32bit that's why it is necessary to
record information about architecture that other code can read it and
properly pass it to TF-A and start in 64bit or 32bit mode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-23 09:48:36 +02:00
Michal Simek
3972ae65e4 arm64: zynqmp: Add missing year in Kria dts files
DT files have been added this year but forgot to update it that's why do it
in separate patch now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
9899f3e6b9 arm64: zynqmp: Add psgtr description to zc1751 dc1 board
Wire psgtr for zc1751 dc1 board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
52caf2c12b arm64: zynqmp: Remove gpio from aliases list
It is not recommended to have aliases for gpio. In past it was used in
Linux for assigning numbers via sysfs which is deprecated and libgpiod
should be used instead.
In U-Boot this number is used for seq number but gpio offset are not
counted from this number. That's why having these aliases only for seq
number is not needed. As is done in Linux it is the best to use full gpio
name instead of sequence number which depends on sequence in binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
83dc13384b arm64: zynqmp: Enable USB3.0 for dc2/dc3
Both boards are usb3.0 capable. dc3 was also missing enabling dwc3* nodes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
cb4380abfd arm64: zynqmp: Update usb dwc3 DT description
Align USB nodes with the latest dt-bindings. It is adding resets, new
interrupt and also some quirks.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
b6d8d4b100 arm64: zynqmp: Use overlay sugar syntax for Kria SOM
dtc supports new sugar syntax which is easier compare to previous one
that's why also covert overlays for SOM to it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
3dbd53144c arm64: zynqmp: Remove revA compatibility string from kv260 revB/1
kv260-revB is different compare to revA (usbhub is wired via i2c) that's
why remove revA compatible string.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Zhengxun
2b157d8127 clk: zynq: Add clock wizard driver
The Clocking Wizard IP supports clock circuits customized
to your clocking requirements. The wizard support for
dynamically reconfiguring the clocking primitives for
Multiply, Divide, Phase Shift/Offset, or Duty Cycle.

Limited by U-Boot clk uclass without set_phase API, this
patch only provides set_rate to modify the frequency.

Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
4d3de8abff arm64: zynqmp: Add support for 64bit addresses in its
Xilinx ZynqMP supports also addresses above 4GB (32bit) that's why also
generate u-boot.its with 64bit load/entry addresses to also support
different configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
6a2ce6ec24 arm64: zynqmp: Sync psgtr location on zcu104/zcu111/zc1751-dc1
psgtr node should be below pinctrl for easier comparion among dts files.
That's why move that nodes to different location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
e0f99280ee arm64: zynqmp: Remove information about dma clock on zcu106
Clock setting is not static anymore that's why it depends on firmware setup
that's why remove this comment.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
d245d0dfd8 arm64: zynqmp: Remove unused property from SD/USB
Linux kernel is not using these properties that's why they can be removed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
0c79419d35 arm64: zynqmp: Remove can aliases from zc1751
Networking subsystem is not using aliases that's why remove them for CAN
devices. There is also no any other Xilinx ZynqMP DT file with them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
43086886ad arm64: zynqmp: Remove si5328 and si5382 nodes
There are no drivers for these devices that's why remove that nodes
completely. This change is done based on Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210308115437.2232847-1-quanyang.wang@windriver.com
2021-06-23 09:48:35 +02:00
Michal Simek
531abcb71e xilinx: Convert xlnx,eeprom property to nvmem alias
Convert all boards to use nvmem alias instead of xlnx,eeprom. The change is
done based on discussion in the link below.

Link: https://lore.kernel.org/r/CAL_JsqLMDqpkyg-Q7mUfw-XH67-v068Q6e9wTq2UOoN=0-_coQ@mail.gmail.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Srinivas Neeli
ee6b3c54e9 arm64: zynqmp: rtc: Update rtc calibration value
As per the design specification
"The 16-bit Seconds Calibration Value represents the number of
 Oscillator Ticks that are required to measure the largest time
 period that is less than or equal to 1 second.
 For an oscillator that is 32.768 KHz, this value will be 0x7FFF."

Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
5fa9672248 arm64: zynqmp: Sync psgtr location on zcu100/zcu106
psgtr node should be below pinctrl for easier comparion among dts files.
That's why move that nodes to different location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
abd30371d3 arm64: zynqmp: Sync dp port location on zc1751 dc4
Historically dpdma and dpsub are placed at the end of files. Move nodes
there for easier comparison among dts files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
af04516992 arm64: zynqmp: Remove unused dp_aclk clock
dp_aclk is not used anywhere that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
70fbcdb825 arm64: zynqmp: Remove addition newline from zc1751 dc1
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
184309b8c6 arm64: zynqmp: Add maximum-speed property for dwc3 nodes
dwc3 can be used only for higher speeds than super-speed that's why
explicitly set it up.
This is also aligned with other ZynqMP dts files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
7c3ad8f6a3 arm64: zynqmp: Remove additional header from zc1232 DT
Remove unused phy.h from zc1232 DTS.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
02860e1562 zynqmp: Remove u-boot,dm-pre-reloc for uart instances
Uarts already have u-boot,dm-pre-reloc via zynqmp.dtsi that's why there is
no need to have them in platform DT files too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
653736c243 zynqmp: Pass bl32 entry to TF-A via xilinx handoff structure
There is need to pass entry about secure OS when bl32_entry is defined.
Currently only 64bit support is added but /fit-images node have been
extended to also record if this is 32bit or 64bit secure OS. When this is
tested the code will be update to support this configuration too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
84c88d6ef2 zynqmp: Generate u-boot.its also with TEE dynamically
The first change is to trying to find out TF-A load address based on
reading elf file. Expectation is that bl31.bin is in the same folder as
bl31.elf. It brings new flexibility to place TF-A to any address (DDR
included).

And also enable TEE generation also with TEE configuration.
Expecation is the same as above that tee.bin and tee.elf are in the same
folder.

User has to just define link to BL31/BL32 binary files and the rest should
be handled by the script.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
ce39ee28ec zynqmp: Do not place u-boot to reserved memory location
TF-A and SecureOS can allocate the part of DDR for self but U-Boot is not
handling this configuration that the part of memory is reserved and
shouldn't be used by U-Boot. That's why read all reserved memory locations
and don't use it.
The code was taken from commit 4a1b975dac ("board: stm32mp1: reserve
memory for OP-TEE in device tree") and commit 1419e5b516 ("stm32mp:
update MMU config before the relocation") which is used by stm32 and does
the job properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
43ef4c82fe zynqmp: Enable regulators
Enable command and fixed regulators. XDP platform is using them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
447fb8db02 arm64: zynqmp: Update Copyright years to 2021
Trivial change for all files I have touched recently.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
eca0376b54 arm64: zynqmp: Add label for zynqmp_ipi
Add label which is used by bootloader for adding bootloader specific flag.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3dc8416abdd3498e61edcd83830a12af295c5c6d.1611224800.git.michal.simek@xilinx.com
2021-06-23 09:48:35 +02:00
Michal Simek
f2b5dd38de arm64: zynqmp: Move DP nodes to the end of file (zcu106)
Just sync it with others for easier comparison.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
fee3e307f2 arm64: zynqmp: Add reset description for sata
Sata needs to get reset before configuration that's why add property for it
there.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Stefano Stabellini
ce42bd2fa3 arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi
The SMMU is disabled in device tree so this change has no impact.
The benefit is that this way it is in sync with xen.dtsi. Xen enables
the SMMU and makes use of it.

Signed-off-by: Stefano Stabellini <stefano.stabellini@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
d9be8b4f2f arm64: zynqmp: Disable CCI by default
There is no reason to have CCI no enabled by default. Enable it when your
system configuration requires it. In Xilinx configuration flow this is
work for Device Tree Generator which reads information from HW Design
configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
1242a6b13d arm64: zynqmp: Update psgtr clocks index for boards
Update the psgtr clock indexing for couple of zynqmp boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
476588c9b4 arm64: zynqmp: Handle MMC seq number based on boot device
K26 has EMMC and SD and default 0 is not working when system is booting out
of SD which is controller 1. Add controller autodetection via
mmc_get_env_dev(). The same code is used for distro_boot selection done in
board_late_init(). bootseq variable can't be reused because this is called
so late.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
02ac1553b8 arm64: zynqmp: Add psu_init_gpl for k26 boards
Add psu_init_gpl file for getting SPL to work directly from the tree.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
767aa16d41 ARM: zynq: Rename bus to be align with simple-bus yaml
Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI
point-to-point channels for communicating addresses, data, and response
transactions between master and slave clients. This ARM AMBA 3.0..."

Issues are reported as:
.. amba: $nodename:0: 'amba' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>From schema:
../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml

Similar change has been done for Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com
2021-06-23 09:48:35 +02:00
Michal Simek
351b9f5f95 arm64: zynqmp: Enable gpio driver for zcu1275/zcu1285
Enable gpio driver on these boards. GPIOs can be used on any board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
ddf8deabc3 arm64: zynqmp: Add support for SVD devices
SVDs  are using different name which can't be handled via zynqmp_devices
structure. That's why introduce zynqmp_detect_svd_name() which checks ID
code for these devices and show proper name for them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
ab09e16d5a arm64: zynqmp: Enable EFI secure boot
Enabling EFI secure boot which is required for EBBR specification.
Enabling this will fix
"RT.SetVariable - Create one Time Base Auth Variable, the expect return
status should be EFI_SUCCESS"

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
T Karthik Reddy
122ca834f2 arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc
CONFIG_ZYNQMP_FIRMWARE enables zynqmp firmware driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
2021-06-23 09:48:35 +02:00
Ashok Reddy Soma
aee1ed87e7 arm64: zynqmp: Fix application loading on R5 core1
From U-Boot, loading application on RPU core 0 is fine but loading on
core 1 is not handled properly. Lock-step mode needs both the R5 cores
to be initialized and it is working fine. Whereas in SPLIT mode individual
R5 cores needs to be initialized as they need to execute differenet
applications. Handle both these lock-step and split modes by propagating
mode and RPU core number(4 for RPU0 and 5 for RPU1) for various functions
and by adding conditions in those functions.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
e246dc49cf ARM: zynq: Fix OCM mapping to be aligned with binding on zc702
The Linux commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to
json-schema") converted binding to yaml and some missing required
properties started to be reported. Align binding based on it.

The patch is fixing these warnings:
.../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property
>From schema: .../Documentation/devicetree/bindings/sram/sram.yaml

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/87c02786ccd8d7827827a9d95a8737bb300caeb0.1606397101.git.michal.simek@xilinx.com
2021-06-23 09:48:35 +02:00