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9 commits

Author SHA1 Message Date
Meenakshi Aggarwal
3a187cff7a armv8: lx2162a: Add Soc changes to support LX2162A 
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.

LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
[Fixed whitespace errors]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
 2020-12-10 13:56:39 +05:30
Joakim Tjernlund
73af094c84 ddr: fsl: Impl. Erratum A008109 
Impl. erratum as descibed in errata doc.
Enable A008109 for T1040 and T1024

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
 2020-06-04 18:53:20 +05:30
Rajesh Bhagat
32413125b3 configs: fsl: move DDR specific defines to Kconfig 
Moves below DDR specific defines to Kconfig:

CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESH

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 2019-03-03 20:56:01 +05:30
Priyanka Jain
4909b89ec7 armv8: lx2160a: Add LX2160A SoC Support 
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
 2018-12-06 14:37:19 -08:00
York Sun
51370d5618 ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS 
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.

Signed-off-by: York Sun <york.sun@nxp.com>
 2017-01-04 19:40:52 -05:00
York Sun
66e399b68d ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig 
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.

Signed-off-by: York Sun <york.sun@nxp.com>
 2017-01-04 19:40:49 -05:00
York Sun
63659ff317 powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig 
Use Kconfig to select errata workaround.

Signed-off-by: York Sun <york.sun@nxp.com>
 2017-01-04 19:40:46 -05:00
York Sun
ba1b6fb5cc arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig 
Use Kconfig to select errata workaround.

Signed-off-by: York Sun <york.sun@nxp.com>
 2017-01-04 19:40:42 -05:00
York Sun
d26e34c4c4 fsl_ddr: Move DDR config options to driver Kconfig 
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
 2017-01-04 19:40:41 -05:00