Commit graph

1095 commits

Author SHA1 Message Date
Pratyush Yadav
bd8c8dcd4d spi: cadence-qspi: Do not calibrate when device tree sets read delay
If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.

This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It needs a read delay of 4 in
octal DTR mode. But since the calibration procedure is run before the
flash is switched in octal DTR mode, it yields a read delay of 2. A
value of 4 works for both octal DTR and legacy modes.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28 11:56:53 +05:30
Pratyush Yadav
5752d6ae8d spi: spi-mem: add spi_mem_dtr_supports_op()
spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.

This means that controller drivers that want to support DTR mode can't
use spi_mem_default_supports_op(). Driver authors have to roll their own
supports_op() function and mimic the buswidth checks. Or even worse,
driver authors might skip it completely or get it wrong.

Add spi_mem_dtr_supports_op(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28 11:56:06 +05:30
Pratyush Yadav
d15de62301 spi: spi-mem: allow specifying a command's extension
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode. When it is "hex" an additional opcode byte based
is sent with the command whose value can be anything.

So, make opcode a 16-bit value and add a 'nbytes', similar to how
multiple address widths are handled.

All usages of sizeof(op->cmd.opcode) also need to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28 11:55:11 +05:30
Pratyush Yadav
a1eb40b70b spi: spi-mem: allow specifying whether an op is DTR or not
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28 11:53:48 +05:30
Zhengxun
0d7066bce2 spi: Add MXIC controller driver
Add a driver for Macronix SPI controller IP.

This patch referred from linux spi-mxic.c. The difference from the
linux version is described here.

1. To adapt uboot spi framework, modify some functions naming.

2. Remove the incompatible functions of Uboot.

3. Add dummy byte recalculattion function to support dummy buswidth
   not align data buswidth operation.(ex: 1-1-4, 1-1-8)

4. Add Octal mode support.

Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: fixed file permission, comment line, kconfig]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-25 20:59:45 +05:30
Daniil Stas
88f7ca03b4 spi: stm32_qspi: Fix short data write operation
TCF flag only means that all data was sent to FIFO. To check if the
data was sent out of FIFO we should also wait for the BUSY flag to be
cleared. Otherwise there is a race condition which can lead to
inability to write short (one byte long) data.

Signed-off-by: Daniil Stas <daniil.stas@posteo.net>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-06-18 08:39:45 +02:00
Ashok Reddy Soma
2ffa653798 spi: zynqmp_gqspi: Fix write issue
Enable manual start in zynqmp_qspi_fill_gen_fifo().
Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of
GQSPI_IXR_GFEMTY_MASK.

Add dummy write to genfifo register in chipselect.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
2021-06-11 09:24:58 +02:00
Grzegorz Jaszczyk
9c84159ce1 spi: kirkwood: prevent limiting speed to 0
After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2
("spi: kirkwood: prevent configuring speed exceeding max controller freq")
the spi frequency could be set to 0 on platform where spi-max-frequency
is not defined (e.g. on armada-388-gp). Prevent limiting speed in
mentioned cases.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Marcin Wojtas <marcin@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00
Marcin Wojtas
562f8d5b36 spi: kirkwood: prevent configuring speed exceeding max controller freq
This patch adds a limitation in the kirkwood_spi driver
set_speed hook, which prevents setting too high transfer
speed.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00
Ken Ma
037818c544 spi: kirkwood: support extended baud rates
The Armada SoC family implementation of this SPI hardware module has
extended the configuration register to allow for a wider range of SPI
clock rates. Specifically the Serial Baud Rate Pre-selection bits in the
SPI Interface Configuration Register now also use bits 6 and 7 as well.

Modify the baud rate calculation to handle these differences for the
Armada case. Potentially a baud rate can be setup using a number of
different pre-scalar and scalar combinations. This code tries all
possible pre-scalar divisors (8 in total) to try and find the most
accurate set.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-16 06:48:45 +02:00
Dylan Jhong
1412b8d48a atcspi200: Add timeout mechanism in spi_xfer()
Adding timeout mechanism to avoid spi driver from stucking
in the while loop in __atcspi200_spi_xfer().

Signed-off-by: Dylan Jhong <dylan@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-05 16:12:14 +08:00
Michal Simek
b00bad9dc8 spi: zynqmp: Remove gd reference
gd is not used in this file that's why doesn't make sense to declare it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-04-29 14:48:31 +02:00
Tom Rini
db8b46120a Xilinx changes for v2021.07
net:
 - Fix gem PCS support
 
 spi:
 - Small trivial fixes
 
 zynq:
 - Enable time/timer commands
 - Update bitmain platform
 - Several DT changes
 
 zynqmp:
 - Update clock driver
 - mini config alignments
 - Add/update psu_init for zcu208/zcu216/zc1275
 - Several DT changes
 - Enable efi debug command (also for Versal)
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Merge tag 'xilinx-for-v2021.07' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.07

net:
- Fix gem PCS support

spi:
- Small trivial fixes

zynq:
- Enable time/timer commands
- Update bitmain platform
- Several DT changes

zynqmp:
- Update clock driver
- mini config alignments
- Add/update psu_init for zcu208/zcu216/zc1275
- Several DT changes
- Enable efi debug command (also for Versal)
2021-03-31 09:47:30 -04:00
T Karthik Reddy
d999a7b7b6 spi: xilinx_spi: Trivial fixes in axi qspi driver
Use __func__ instead for function name in debug.
Use Linux style u32 instead of uint32_t.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30 12:03:24 +02:00
T Karthik Reddy
346df7d4fa spi: spi-uclass: Add support to manually relocate spi memory ops
Add spi memory operations to relocate manually when
CONFIG_NEEDS_MANUAL_RELOC is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-03-27 16:26:48 +13:00
Patrice Chotard
e48ec51b43 spi: stm32_qspi: Add WATCHDOG_RESET in _stm32_qspi_read_fifo()
In case of reading large area and memory-map mode is misconfigured
(memory-map size declared lower than the real size of the memory chip)
watchdog can be triggered.

Add WATCHDOG_RESET() in _stm32_qspi_read_fifo to fix it.

Issue reproduced with stm32mp157c-ev1 board and memory map size set to
1, with following command:
sf read 0xC0000000 0 0x4000000

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-11 16:59:16 +01:00
Adam Ford
90d76f812b spi: nxp_fspi: Fix error reporting
On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
rate the clock was able to set.  When checking for errors, it only
checks that it is not NULL.  Since positive numbers are not errors,
only check for negative numbers when handling errors.

Fixes: 383fded70c ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 15:09:38 +05:30
Marek Vasut
c1d264e84e spi: imx: Implement set_speed
The set_speed() callback should configure the bus speed, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-26 13:25:21 +05:30
Tom Rini
cbe607b920 Xilinx changes for v2021.04-rc3
qspi:
 - Support for dual/quad mode
 - Fix speed handling
 
 clk:
 - Add clock enable function for zynq/zynqmp/versal
 
 gem:
 - Enable clock for Versal
 - Fix error path
 - Fix mdio deregistration path
 
 fpga:
 - Fix buffer alignment for ZynqMP
 
 xilinx:
 - Fix reset reason clearing in ZynqMP
 - Show silicon version in SPL for Zynq/ZynqMP
 - Fix DTB selection for ZynqMP
 - Rename zc1275 to zcu1275 to match DT name
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Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.04-rc3

qspi:
- Support for dual/quad mode
- Fix speed handling

clk:
- Add clock enable function for zynq/zynqmp/versal

gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path

fpga:
- Fix buffer alignment for ZynqMP

xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
2021-02-23 10:45:55 -05:00
Brandon Maier
d9aa19efa8 spi: zynqmp_gqspi: fix set_speed bug on multiple runs
If zynqmp_qspi_set_speed() is called multiple times with the same speed,
then on the second call it will skip recalculating the baud_rate_val as
it assumes the speed is already configured correctly. But it will still
write the baud_rate_val to the configuration register and call
zynqmp_gqspi_set_tapdelay(). Because it skipped recalculating the
baud_rate_val, it will use the initial value of 0 . This causes the
driver to run at maximum speed which for many spi flashes is too fast and
causes data corruption.

Instead only write out a new baud_rate_val if we have calculated the
correct baud_rate_val.

This opens up another issue with the "if (speed == 0)", we don't save
off the new plat->speed_hz value when setting the baud rate on the
speed=0 path. Instead mimic what the Linux zynqmp gqspi driver does, and
have speed==0 just use the same calculation as a normal speed. That will
cause the baud_rate_val to use the slowest speed possible, which is the
safest option.

Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com>
CC: jagan@amarulasolutions.com
CC: michal.simek@xilinx.com
CC: Ashok Reddy Soma <ashokred@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23 14:56:59 +01:00
Michal Simek
9b7aac7536 clk: zynq: Add dummy clock enable function
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c11 ("clk: fixed_rate: add dummy enable() function").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23 14:56:59 +01:00
Tom Rini
2ae80437fb Merge branch '2021-02-02-drop-asm_global_data-when-unused'
- Merge the patch to take <asm/global_data.h> out of <common.h>
2021-02-15 10:16:45 -05:00
Mathew McBride
fd20097336 spi: fsl_qspi: apply the same settings for LS1088 as LS208x
The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL
workaround as the LS208x and also has a 64 byte TX buffer.

With the previous settings SPI-NAND reads over AHB were
corrupted.

Fixes: 91afd36f38 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API")
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Mathew McBride
6b4eb604ea spi: fsl_qspi: Ensure width is respected in spi-mem operations
Adapted from kernel commit b0177aca7aea
From: Michael Walle <michael@walle.cc>

Make use of a core helper to ensure the desired width is respected
when calling spi-mem operators.

Otherwise only the SPI controller will be matched with the flash chip,
which might lead to wrong widths. Also consider the width specified by
the user in the device tree.

Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller")
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mathew McBride <matt@traverse.com.au> [adapt for U-Boot]
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08 14:01:18 +05:30
Brandon Maier
f1fd79afad spi: zynqmp_gqspi: support dual and quad mode
The dm_spi_ops.xfer() API does not support dual and quad SPI modes. It
also doesn't allow the zynqmp_gqspi driver to calculate the correct
number of dummy cycles for some NOR ops (as doing so also requires the
buswidth).

Port the zynqmp_gqspi driver to spi_controller_mem_ops, which gives us
the buswidth values to correctly support all SNOR_PROTO_X_X_X commands
and to properly calculate dummy cycles.

Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com>
CC: jagan@amarulasolutions.com
CC: michal.simek@xilinx.com
CC: Ashok Reddy Soma <ashokred@xilinx.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-03 13:36:44 +01:00
Simon Glass
401d1c4f5d common: Drop asm/global_data.h from common header
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-02 15:33:42 -05:00
SkyLake.Huang
7a49d61742 spi: mtk_snor: add support for MTK SPI NOR controller
This patch adds support for MTK SPI NOR controller, which you
can see on mt7622 & mt7629.

1. This controller is designed only for SPI NOR. We can't adjust
its bus clock dynamically. Set clock in dts instead.
2. This controller only supports 1-1-1 write mode.
3. Remove mtk_snor_match_read() since upper SPI-MEM layer already
handles command.
4. sf read/write/update commands are tested with this driver.

Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
2021-01-29 10:35:14 -05:00
Tom Rini
c99be953e7 - MIPS: add support for Mediatek MT7620 SoCs
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Merge tag 'mips-pull-2021-01-24' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips

- MIPS: add support for Mediatek MT7620 SoCs
2021-01-25 14:38:40 -05:00
Weijie Gao
2db6fba051 spi: add spi controller support for MediaTek MT7620 SoC
This patch adds spi controller support for MediaTek MT7620 SoC.

The SPI controller supports two chip selects. These two chip selects are
implemented as two separate register groups, but they share the same bus
(DI/DO/CLK), only CS pins are dedicated for each register group.
Appearently these two register groups cannot operates simulataneously so
they are implemented as one controller.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:26 +01:00
Marek Vasut
38b92ca196 spi: imx: Use clock framework if enabled
In case the clock framework is enabled, enable the SPI controller clock
and obtain max frequency from the clock framework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
2021-01-23 13:40:29 +01:00
Marek Vasut
6cd4f48b64 spi: imx: Define register bits in the driver
The CSPI/ECSPI register bits do not differ between newer SoCs, instead
of having multiple copies of the same thing for each iMX SoC, define
the bits in the driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
2021-01-23 13:40:29 +01:00
Adam Ford
5fb6b82471 spi: nxp_fspi: Enable support for nxp,imx8mm-fspi
The i.MX8M Mini can use the FlexSPI driver.  Add support
for it to the driver.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-01-23 13:40:29 +01:00
Dario Binacchi
b0db69b4e1 dm: fix build errors generated by last merges
Something was wrong in the merge process into the mainline.
Some added patches access driver structure fields and functions that
have been modified by previous patches.
The patch renames:
 - dev_get_platdata to dev_get_plat
 - dev_get_uclass_platdata to dev_get_uclass_plat
 - ofdata_to_platdata to of_to_plat
 - plat_data_alloc_size to plat_auto
 - priv_auto_alloc_size to priv_auto
 - video_uc_platdata to video_uc_plat

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-15 13:12:38 -05:00
Patrick Delaunay
162f5888e7 spi: stm32_qspi: migrate trace to dev and log macro
Change debug/pr_* to log_* or dev_* macro and define LOG_CATEGORY.

Remove the "%s:" __func__  header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-13 09:52:58 +01:00
Patrick Delaunay
7a41cb50ce spi: stm32_spi: migrate trace to dev and log macro
Change debug/pr_debug to log_debug or dev_dbg macro and
define LOG_CATEGORY.

Remove the "%s:" __func__  header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-13 09:52:58 +01:00
Vignesh Raghavendra
f3f83ad4ca spi: omap3_spi: Fix speed and mode selection
McSPI IP provides per CS specific speed and mode selection. Therefore it
is possible to apply these settings only after CS is known. But
set_speed and set_mode can be called without bus being claimed, this
would lead driver to set up wrong CS (or previously used CS).

Fix this by apply set_speed and set_mode only if bus is already claimed.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-01-12 10:21:41 +05:30
Ovidiu Panait
705082d4b1 spi: ti_qspi: Fix "spi-max-frequency" error path in ti_qspi_ofdata_to_platdata
struct ti_qspi_priv->max_hz is declared as unsigned int, so the following
error path check will always be false, even when "spi-max-frequency"
property is invalid/missing:
  priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
  if (priv->max_hz < 0) {
    ...
  }

Replace the fdtdec call with dev_read_u32_default() and use 0 as the
default value. Error out if max_hz is zero.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2021-01-12 10:21:41 +05:30
Tom Rini
bc0b99bd8b Xilinx changes for v2021.04
arm64:
 - DT updates
 
 microblaze:
 - Add support for NOR device support
 
 spi:
 - Fix unaligned data write issue
 
 nand:
 - Minor code change
 
 xilinx:
 - Fru fix in limit calculation
 - Fill git repo link for all Xilinx boards
 
 video:
 - Add support for seps525 spi display
 
 tools:
 - Minor Vitis file support
 
 cmd/common
 - Minor code indentation fixes
 
 serial:
 - Uartlite debug uart initialization fix
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Merge tag 'xilinx-for-v2021.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.04

arm64:
- DT updates

microblaze:
- Add support for NOR device support

spi:
- Fix unaligned data write issue

nand:
- Minor code change

xilinx:
- Fru fix in limit calculation
- Fill git repo link for all Xilinx boards

video:
- Add support for seps525 spi display

tools:
- Minor Vitis file support

cmd/common
- Minor code indentation fixes

serial:
- Uartlite debug uart initialization fix
2021-01-06 07:57:33 -05:00
Tom Rini
b11f634b1c Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
 dtoc: Tidy up and add more tests
 ns16550 code clean-up
 x86 and sandbox minor fixes for of-platdata
 dtoc prepration for adding build-time instantiation
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Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next

Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
2021-01-05 22:34:43 -05:00
Tom Rini
720620e691 Prepare v2021.01-rc5
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Merge tag 'v2021.01-rc5' into next

Prepare v2021.01-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05 16:20:26 -05:00
Simon Glass
bdf8fd76c0 dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIAS
We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but
in every other case we just use DM_. Update the alias macros to use the
DM_ prefix.

We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro
is widely used and there is at least some benefit to indicating it us a
U-Boot driver, particularly for code ported from Linux. So for now, let's
keep that name.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:26:35 -07:00
Simon Glass
f10643cf8a dm: core: Access device ofnode through functions
At present ofnode is present in the device even if it is never used. With
of-platdata this field is not used, so can be removed. In preparation for
this, change the access to go through inline functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:24:41 -07:00
Simon Glass
7d14ee443c dm: core: Use dev_has_ofnode() instead of dev_of_valid()
We have two functions which do the same thing. Standardise on
dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in
normal operation: it is either null or missing.

Also move the functions into one place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05 12:24:41 -07:00
Simon Glass
a53f6fad7e x86: spl: Move priv/plat structs to headers
With the new of-platdata, these need to be available to dt_platdata.c
so must be in header files. Move them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:24:41 -07:00
Simon Glass
0fd3d91152 dm: Use access methods for dev/uclass private data
Most drivers use these access methods but a few do not. Update them.

In some cases the access is not permitted, so mark those with a FIXME tag
for the maintainer to check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
2021-01-05 12:24:40 -07:00
T Karthik Reddy
90217487a1 spi: zynqmp_gqspi: Fix unaligned data writes issue
When unaligned 3 bytes data write operation is performed, 3rd byte
is being over written by 1st byte of 3 bytes data. This patch
fixes it.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-01-04 10:51:27 +01:00
Niel Fourie
fc314300dd dm: spi: Fix spi_free_slave() freed memory write
Remove setting slave->dev to NULL after the device_remove() call.

The slave pointer points to dev->parent_priv, which has already
been freed by device_free(), called from device_remove() in the
preceding line. Writing to slave->dev may cause corruption of the
dlmalloc free chunk forward pointer of the previously freed chunk.

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-22 20:39:26 -07:00
Ovidiu Panait
741280e9ac spi: spi-uclass: Fix spi_claim_bus() speed/mode setup logic
Currently, when different spi slaves claim the bus consecutively using
spi_claim_bus(), spi_set_speed_mode() will only be executed on the first
two calls, leaving the bus in a bad state starting with the third call.

This patch drops spi_slave->speed member and adds caching of bus
speed/mode in dm_spi_bus struct. It also updates spi_claim_bus() to call
spi_set_speed_mode() if either speed or mode is different from what the
bus is currently configured for. Current behavior is to only take into
account the speed, but not the mode, which seems wrong.

Fixes: 60e2809a84 ("dm: spi: Avoid setting the speed with every transfer")
Reviewed-by: Simon Glass <sjg@chromium.org>
Reported-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reported-by: Moshe, Yaniv <yanivmo@amazon.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-12-22 20:39:26 -07:00
Ovidiu Panait
add685fb6d test: spi: Add sandbox_spi_get_{speed, mode} interface
Introduce sandbox_spi_get_{speed, mode} public interface to retrieve the
sandbox spi bus internal state. They are meant to be used in sandbox spi
testcases.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-22 20:39:26 -07:00
Ovidiu Panait
2da1800456 spi: sandbox_spi: Implement speed/mode setup
Implement sandbox_spi_set_{speed, mode} routines, to be able to keep track
of the current bus speed/mode. This will help determine whether the values
passed from dm_spi_claim_bus() are valid.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-12-22 20:39:25 -07:00
Ovidiu Panait
1dc53ce71d sandbox: test: Add a second SPI slave on sandbox_spi bus
Place a second spi slave on the sandbox_spi bus, to be used by the
spi_claim_bus() testcase we are about to introduce. We need to make sure
that jumping between slaves calling spi_claim_bus() sets the bus speed and
mode appropriately. Use different max-hz and mode properties for this new
slave.

Also, update sandbox_spi cs_info call to allow activity on CS0/CS1 and
adapt dm_test_spi_find() testcase for this new setup.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-22 20:39:25 -07:00
Ovidiu Panait
1f6d618bb1 sandbox: spi: Drop unused sandbox_spi_parse_spec function
Commit 1289e96797 ("sandbox: spi: Drop command-line SPI option") dropped
support for specifying SPI devices on the command line, removing the only
user of sandbox_spi_parse_spec(). Remove the function too.

Fixes: 1289e96797 ("sandbox: spi: Drop command-line SPI option")
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-22 20:39:25 -07:00
Simon Glass
991759196f dm: Drop the unused arg in uclass_find_device_by_seq()
Now that there is only one sequence number (rather than both requested and
assigned ones) we can simplify this function. Also update its caller to
simplify the logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18 20:32:21 -07:00
Simon Glass
6d83c74db7 spi: Update for new sequence numbers
Use the new sequence number in all cases. Drop the rockchip case because
the sequence number should be 0 anyway, and assigning to the sequence
number is not permitted.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18 20:32:21 -07:00
Simon Glass
8b85dfc675 dm: Avoid accessing seq directly
At present various drivers etc. access the device's 'seq' member directly.
This makes it harder to change the meaning of that member. Change access
to go through a function instead.

The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18 20:32:21 -07:00
Pengpeng Chen
24f2794232 spi: ca_sflash: Add CAxxxx SPI Flash Controller
Add SPI Flash controller driver for Cortina Access
CAxxxx SoCs

Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Vignesh R <vigneshr@ti.com>
CC: Tom Rini <trini@konsulko.com>
[jagan: rebase on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
fec7bf0460 spi: dw: Add mem_ops
The designware ssi device has "broken" chip select behaviour [1], and needs
specific manipulation to use the built-in chip select. The existing fix is
to use an external GPIO for chip select, but typically the K210 has SPI3
directly connected to a flash chip with dedicated pins. This makes it
impossible to use the spi_xfer function to use spi, since the CS is
de-asserted in between calls.  This patch adds an implementation of
exec_op, which gives correct behaviour when reading/writing spi flash.

This patch also rearranges the headers to conform to U-Boot style.

[1] https://lkml.org/lkml/2015/12/23/132

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
58875790fd spi: dw: Add support for multiple CTRLR0 layouts
CTRLR0 can have several different layouts depending on the specific device
(dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis.
Update the driver to support three specific configurations: dw-apb-ssi with
SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi.

dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC
SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver
supported before this change. The register layout before version 3.23a is:

|   31 .. 16  |
| other stuff |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 |
| other stuff |  TMOD  |  MODE  |  FRF   |  DFS   |

Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data
frames of 16 bits or less.

In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This
parameter defaults to 16 (resulting in the same layout as prior versions),
but may also be set to 32. To allow setting longer data frame sizes, a new
DFS_32 register was introduced:

|   31 .. 21  | 20 .. 16 |
| other stuff |  DFS_32  |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 |  3 .. 0   |
| other stuff |  TMOD  |  MODE  |  FRF   | all zeros |

The old DFS field no longer controls the data frame size. To detect this
layout, we try writing 0xF to DFS. If we read back 0x0, then this device
has SSI_MAX_XFER_SIZE=32.

dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan
Kendryte K210 SoCs. The layout of ctrlr0 is:

|   31 .. 16  |
| other stuff |

|   15 .. 12  | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 |
| other stuff |   TMOD   |  MODE  |  FRF   | DFS_32 |

The semantics of the fields have not changed since the previous version.
However, SSI_MAX_XFER_SIZE is effectively always 32.

To support these different layouts, we model our approach on the one
which the Linux kernel has taken. During probe, the driver calls an init
function stored in driver_data. This init function is responsible for
determining the layout of CTRLR0, and supplying the update_cr0 function.

The style of and information behind this commit is based on the Linux MMIO
driver for these devices. Specific reference was made to the series adding
support for Intel Keem Bay SoCs [1].

[1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@intel.com/

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
ddd3450f39 spi: dw: Rearrange struct dw_spi_priv
This should reduce the size of the struct, and also groups more similar
fields together.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
934beab882 spi: dw: Remove spi_enable_chip
This function does nothing but wrap dw_write.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
3004034989 spi: dw: Rename registers to match datasheet
A few registers had slightly different names from what is in the datasheet.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Sean Anderson
c785f43ffd spi: dw: Use generic function to read reg address
Using an fdt-specific function causes problems when compiled with a live
tree.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Sean Anderson
13fc44e222 spi: dw: Rename "cs-gpio" to "cs-gpios"
This property is named differently than other SPI drivers with the same
property, as well as the property as used in Linux.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Sean Anderson
1b3dd491e6 spi: dw: Convert calls to debug to dev_*
This allows different log levels to be enabled or disabled depending on the
desired level of verbosity. In particular, it allows for general debug
information to be printed while excluding more verbose logging which may
interfere with timing.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Sean Anderson
caf110798c spi: dw: Fix driving MOSI low while recieving
The resting state of MOSI is high when nothing is driving it. If we drive
it low while recieving, it looks like we are transmitting 0x00 instead of
transmitting nothing. This can confuse slaves (like SD cards) which allow
new commands to be sent over MOSI while they are returning data over MISO.
The return of MOSI from 0 to 1 at the end of recieving a byte can look like
a start bit and a transmission bit to an SD card. This will cause the card
to become out-of-sync with the SPI device, as it thinks the device has
already started transmitting two bytes of a new command. The mmc-spi driver
will not detect the R1 response from the SD card, since it is sent too
early, and offset by two bits. This patch fixes transfer errors when using
SD cards with dw spi.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Patrick Delaunay
46c5391b3d spi: migrate trace to dev and log macro in spi uclass
Define LOG_CATEGORY and change printf and pr_*
to dev_ (when dev is available) or log_ macro.

This patch adds the support of logging feature with log command
(filtering, display of device name in trace) and allows to
suppress traces via the syslog driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:36 +05:30
Simon Glass
8a8d24bdf1 dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
b012ff1f1b dm: treewide: Update 'auto' declarations to be on one line
Fix up the code style for those declarations that should now fit onto one
line, which is all of them that currently do not.

This is needed for dtoc to detect the structs correctly, at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
d1998a9fde dm: treewide: Rename ofdata_to_platdata() to of_to_plat()
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
c69cda25c9 dm: treewide: Rename dev_get_platdata() to dev_get_plat()
Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
caa4daa2ae dm: treewide: Rename 'platdata' variables to just 'plat'
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:08 -07:00
Simon Glass
41575d8e4c dm: treewide: Rename auto_alloc_size members to be shorter
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 08:00:25 -07:00
Tom Rini
63d4607e03 of-platdata and dtoc improvements
sandbox SPL tests
 binman support for compressed sections
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Merge tag 'dm-pull-30oct20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

of-platdata and dtoc improvements
sandbox SPL tests
binman support for compressed sections
2020-10-30 15:24:30 -04:00
Simon Glass
d07f31aea0 x86: apl: Enable SPI flash in TPL with APL_SPI_FLASH_BOOT
At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI
and SPI flash are not enabled for TPL. Add a condition to fix this and
tidy up a build warning in the SPI-flash driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-29 14:42:18 -06:00
Ashok Reddy Soma
17fbb598f6 spi: zynq_qspi: Add function description
Add function description for zynq_qspi_init_hw and zynq_qspi_chipselect.
Fix zqspi to priv in function descriptions.
Change the description of priv as pointer to zynq_qspi_priv structure.
Fix other function descriptions to kernel-doc style.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:33 +01:00
T Karthik Reddy
ea836be1e7 spi: zynq_qspi: Use clk subsystem to get reference qspi clk
Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
T Karthik Reddy
b79a7030c3 spi: zynq_spi: Use clk subsystem to get reference spi clk
Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
T Karthik Reddy
c94b44c64b spi: xilinx_spi: remove unused local variable
Remove unused variable 'count' which is causing warning while
compilation.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:13:32 +01:00
Michal Simek
e1303b2bc1 spi: xilinx_spi: Remove unused variable
Remove unused variable:
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer':
drivers/spi/xilinx_spi.c:254:18: warning: unused variable 'timeout' [-Wunused-variable]
  254 |  u32 reg, count, timeout;
      |                  ^~~~~~~

Fixes: 0c0de58f7b ("spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-27 08:01:36 +01:00
Robert Marko
367ea426a5 spi: Add Qualcomm QUP SPI controller driver
This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s.

Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW.
FIFO and Block modes are supported, no support for DMA mode is planned.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Biju Das
2f220c639a spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility string
Add fallback compatibility string for R-Car Gen3 and RZ/G2.

Also sorted the compatible string as per SoC ID.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Tom Rini
dadc1e3830 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix Octeon SPI driver for Octeon TX2
- Fix and enhance Octeon watchdog driver
- Misc minor enhancements to Octeon TX/TX2
2020-10-16 09:56:15 -04:00
Sean Anderson
d13da03f3b spi: fsl_qspi: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16 09:44:27 -04:00
Sean Anderson
06aaca5158 spi: nxp_fspi: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16 09:44:27 -04:00
Stefan Roese
8a35094faa spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2
Octeon TX2 sets the TB100_EN bit in the config register. We need to use
a fixed 100MHz clock for this as well to work properly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
2020-10-16 13:55:04 +02:00
Tom Rini
0f35d96bfd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Octeon TX: Add NAND driver (Suneel)
- Octeon TX: Add NIC driver driver (Suneel)
- Octeon TX2: Add NIC driver driver (Suneel)
- Armada 8040: Add iEi Puzzle-M80 board support (Luka)
- Armada A37xx SPI: Add support for CS-GPIO (George)
- Espressobin: Use Linux model/compatible strings (Andre)
- Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre)
- Armada A37xx: Small cleanup of config header (Pali)
2020-10-14 13:51:56 -04:00
Alper Nebi Yasak
957a3e5493 treewide: Fix wrong CONFIG_IS_ENABLED() handling
CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix,
e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Some of these were being
fixed every now and then, see:

    commit 71ba2cb0d6 ("board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED")
    commit a5ada25e42 ("rockchip: clk: fix wrong CONFIG_IS_ENABLED handling")
    commit 5daf6e56d3 ("common: console: Fix duplicated CONFIG in silent env callback")
    commit 48bfc31b64 ("MIPS: bootm: Fix broken boot_env_legacy codepath")

Fix all files found by `git grep "CONFIG_IS_ENABLED(CONFIG"` by running
':%s/CONFIG_IS_ENABLED(CONFIG_\(\w+\))/CONFIG_IS_ENABLED(\1)/g' in vim.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-14 11:16:34 -04:00
George Hilliard
2df286390a spi: mvebu_a3700_spi: add support for cs-gpios
The device tree has a way to specify GPIO lines as chip selects.  From
the binding docs:

    So if for example the controller has 2 CS lines, and the cs-gpios
    property looks like this:

    cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;

    Then it should be configured so that num_chipselect = 4 with the
    following mapping:

    cs0 : &gpio1 0 0
    cs1 : native
    cs2 : &gpio1 1 0
    cs3 : &gpio1 2 0

Add support for this, while retaining backward-compatibility with
existing device trees; the driver will preserve existing behavior if a
cs-gpios list is not given, or if a particular line is specified as <0>
(native).

This implementation is inspired by similar implementations in
neighboring drivers for other platforms: atmega, mxc, etc.

Signed-off-by: George Hilliard <ghilliar@amazon.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-10-14 07:55:56 +02:00
Tom Rini
b7e7831e5d Merge branch 'next'
Bring in the assorted changes that have been staged in the 'next' branch
prior to release.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-05 14:10:59 -04:00
Sean Anderson
49dfbe924c spi: zynqmp_gqspi: Fix not calling dev_err with a device
Use `bus` instead of `dev`.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:47 -04:00
Sean Anderson
32bbe5b5d3 spi: sunxi: Fix not calling dev_err with a device
Use `bus` and not `dev`.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-09-30 08:53:45 -04:00
Tom Rini
67ece26d8b Xilinx changes for v2021.01
arm64:
 - Support for bigger U-Boot images compiled with PIE
 
 microblaze:
 - Extend support for LE/BE systems
 
 zynqmp:
 - Refactor silicon ID detection code with using firmware interface
 - Add support for saving variables based on bootmode
 
 zynqmp-r5:
 - Fix MPU mapping and defconfig setting.
 
 xilinx:
 - Minor driver changes: names alignment
 - Enable UBIFS
 - Minor DT and macros fixes
 - Fix boot with appended DT
 - Fix distro boot
 
 cmd:
 - pxe: Add fixing for platforms with manual relocation support
 
 clk:
 - fixed_rate: Add DM flag to support early boot on r5
 
 fpga:
 - zynqmppl: Use only firmware interface and enable SPL build
 
 serial:
 - uartlite: Enable for ARM systems and support endians
 
 mmc:
 - zynq: Fix indentation
 
 net:
 - gem: Support for multiple phys
 - emac: Fix 64bit support and enable it for arm64
 
 kconfig:
 - Setup default values for Xilinx platforms
 - Fix dependecies for Xilinx drivers
 - Source board Kconfig only when platform is enabled
 - Fix FPGA Kconfig entry with SPL
 - Change some defconfig values
 
 bindings:
 - Add binding doc for vsc8531
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Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.01

arm64:
- Support for bigger U-Boot images compiled with PIE

microblaze:
- Extend support for LE/BE systems

zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode

zynqmp-r5:
- Fix MPU mapping and defconfig setting.

xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot

cmd:
- pxe: Add fixing for platforms with manual relocation support

clk:
- fixed_rate: Add DM flag to support early boot on r5

fpga:
- zynqmppl: Use only firmware interface and enable SPL build

serial:
- uartlite: Enable for ARM systems and support endians

mmc:
- zynq: Fix indentation

net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64

kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values

bindings:
- Add binding doc for vsc8531
2020-09-24 08:33:47 -04:00
Michal Simek
54fdef242f xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers
Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in
PL and vice versa. That's why change dependencies and do not limit enabling
just for some platforms.

This is follow up patch based on commit 664e16ce99 ("xilinx: kconfig:
Change Kconfig dependencies for Xilinx drivers").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23 10:31:40 +02:00
Rasmus Villemoes
10a6aa963c spi: mpc8xxx_spi.c: fix cs activate/deactivate
Somewhere between v2020.04 and v2020.07 the mpc8xxx_spi driver broke,
I'm guessing due to this hunk

@@ -559,6 +560,8 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
        if (ret)
                return ret;

+       /* combine the requested flags (for IN/OUT) and the descriptor flags */
+       flags |= desc->flags;
        ret = _dm_gpio_set_dir_flags(desc, flags);

from commit 695e5fd546 ("gpio: update dir_flags management"). But
the blame is mostly on the driver itself which seems rather confused:
The chip select gpios are requested with GPIOD_ACTIVE_LOW, but then in
each activate/deactivate, dm_gpio_set_dir_flags() is called with
merely GPIOD_IS_OUT, and then the driver call set_value(0) for
activate.

That used to work, but with the above hunk, the ACTIVE_LOW setting
from the request becomes persistent, so the gpio driver ends up being
asked to set the value to 1 in mpc8xxx_spi_cs_activate().

So drop the dm_gpio_set_dir_flags() calls in the activate/deactivate
functions, and use a value of 1 to mean "logically enabled".

Ideally, I think we should also drop the GPIOD_ACTIVE_LOW from the
request and make it up to the list of gpio cs in DT to indicate
whether that CS is enabled when driven low (as is of course usually
the case), but that requires changing
arch/powerpc/dts/gdsys/gazerbeam-base.dtsi among others, and I don't
have that hardware to test on. I have, however, tested our
own (mpc8309-based) hardware with this change, and I have also tested
that removing the GPIOD_ACTIVE_LOW from the request and updating our
DT as

-                       gpios = <&spisel 0 0>;
+                       gpios = <&spisel 0 GPIO_ACTIVE_LOW>;

still works.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-09-22 11:05:32 -04:00
Faiz Abbas
afd4f15a39 spi: omap3_spi: Read platform data in ofdata_to_platdata()
Add an ofdata_to_platdata() callback to access dts in U-boot and
access all platform data in it. This prepares the driver for supporting
both device tree as well as static platform data structures in SPL.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15 18:51:53 +05:30
Faiz Abbas
41cf3cb39d arm: mach-omap2: am33xx: Add device structure for spi
Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-09-15 18:51:53 +05:30
Faiz Abbas
280af01156 spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failures
There are devices which don't use OF_CONTROL or OF_PLATDATA but instead
rely on statically defined platdata. Block dm_scan_fdt_dev() with both
configs to avoid build failures under this condition.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-09-15 18:51:53 +05:30
Masahiro Yamada
702e57e113 treewide: convert devfdt_get_addr_ptr() to dev_read_addr_ptr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To help this tedious work, this commit converts devfdt_get_addr_ptr()
to dev_read_addr_ptr() by coccinelle. I also removed redundant casts
because dev_read_addr_ptr() returns an opaque pointer.

To generate this commit, I ran the following semantic patch
excluding include/dm/.

  <smpl>
  @@
  type T;
  expression dev;
  @@
  -(T *)devfdt_get_addr_ptr(dev)
  +dev_read_addr_ptr(dev)
  @@
  expression dev;
  @@
  -devfdt_get_addr_ptr(dev)
  +dev_read_addr_ptr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-22 08:53:37 -06:00
Tom Rini
bb3694d5b1 - doc: fix qemu-mips build instructions
- MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
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Merge tag 'mips-pull-2020-08-03' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips

- doc: fix qemu-mips build instructions
- MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
2020-08-04 11:07:16 -04:00
Simon Glass
8b69e629dc spi: Drop duplicate dm.h inclusion
We only need to include this header once. Drop the duplicate.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00