Up till now the fixed rate clock ('osc') has been added to UCLASS_CLK
without declaring struct clk. As a result it was only accessible by
iterating the udevice's uclass list.
This is a problem for clock code, which operates on pointers to struct
clk (like clk_get_rate()), not udevices.
After this change struct clk is accessible from udevice and udevice from
struct clk.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This check requires the struct clk passed to .get_rate() to be always
cleared out as any clock with valid ID causes -EINVAL return value.
The return code of fixed clocks shall always be returned.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To enable USB support in U-Boot, add the required clock and reset gates
to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will
pick them up from there automatically.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This patch solves the following warnings:
drivers/clk/clk_stm32mp1.c: In function 'stm32mp1_clk_get_parent':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
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Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-boot
- Add Ethernet support for STM32MP1
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
Trying to bring up uSDHC2 the following error message was observed:
MMC: imx8_clk_set_rate(Invalid clk ID #60)
imx8_clk_set_rate(Invalid clk ID #60)
usdhc@5b030000 - probe failed: -22
This commit fixes this by properly setting resp. clocks.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
ETHCK_K is the identifier the kernel clock for ETH in kernel
binding, selected by ETHKSELR / gated by ETHCKEN = BIT(7).
U-Boot driver need to use the same identifier, so change ETHCK
to ETHCK_K.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
This adds a clock driver to support the GEMGXL management IP block
found in FU540 SoCs to control GEM TX clock operation mode for
10/100/1000 Mbps.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
- some fix for rk3399-puma;
- rockchip script make_fit_atf.py cleanup
- Enable TPL for rk3399 orangepi and nanopi4;
- add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
The G12A PCIE PLL clock was introduced in Linux 5.2-rc1, and is needed
for USB to operate, add basic support for it and associated gates.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This patch adds the rate for UART1 and UART3 the same way
as already implemented for UART0 and UART2.
This is required for boards, which have their console output
on these UARTs.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Some DM drivers have hardcoded clk_enable calls when handling
clocks (for example the fsl_esdhc driver).
To work with these drivers, add an enable method to the MCP83xx clock
driver (which does nothing, because the clocks are always enabled).
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
clk_get_by_index_tail() now handle common clk get by index
code so use it from clk_get_by_indexed_prop().
Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Getting a CLK by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process CLK operation for child
without udevice but with ofnode.
So add clk_get_by_index_nodev() and move the common code
in clk_get_by_index_tail() to use for clk_get_by_index()
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.
In these scenarios with current order of include files
the fu540-prci driver is unable to find CONFIG_ENV_SIZE.
In file included from arch/riscv/include/asm/u-boot.h:23:0,
from include/dm/of.h:10,
from include/dm/ofnode.h:12,
from include/clk.h:11,
from include/clk-uclass.h:13,
from drivers/clk/sifive/fu540-prci.c:32:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
So, fix consists of changing the order of include files
in fu540-prci.c to include first common.h file.
Cc: Anup Patel <Anup.Patel@wdc.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
------------------------
- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
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Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx
Porting to DM and i.MX8
------------------------
- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
To make it easy to add new clk driver for i.MX8, split
the code into common part and SoC specific part.
Make the get/set/enable non static and introduce a num_clks for
soc_clk_dump, because the arrays are moved to clk-imx8qxp.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Add basic support for the Amlogic G12A clock controller based on
the AXG driver.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In order to support the Amlogic G12A clock controller,
re-architect the clock files into a meson directory.
No functionnal changes.
MAINTAINERS entry is also updated.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
GMAC reset reg offset added by below commit seems to assume
it as EMAC but R40 indeed using GMAC.
"clk: sunxi: Implement EMAC, GMAC clocks, resets"
(sha1: 68620c9698)
So, fix by updating the reg offset for RST_BUS_GMAC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The commit 'f48ef0d81aa837a33020f8d61abb3929ba613774' did break I2C
support because requesting the clock for the I2C ip-block isn't
supported during SPL.
To fixup this we add support requesting clocks for:
- i2c0
- i2c1
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
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Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dm
fdtdec tests and improvements for carve-outs
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32
The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for power
The same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CLK_AHB_GMAC was suppose to be part of previous commit
"clk: sunxi: Implement A10 EMAC clocks" add it so-that
we can get rid of sunxi_set_gate warning on boot message.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms.
This allows the MMCIF driver to set higher clock rate if desired.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The $div and $mul values were swapped in the debug output,
fix this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
