Commit graph

16 commits

Author SHA1 Message Date
Ley Foon Tan
3607a8084a arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC
Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-05-18 10:30:47 +02:00
Marek Vasut
32f99757f4 ARM: socfpga: Repair A10 EMAC reset handling
The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Marek Vasut
f79173280c ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET
This was never used, is not used anywhere and is just in the way
by adding annoying ifdeffery. Get rid of it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Ley Foon Tan
827e6a7e0d arm: socfpga: Add reset driver support for Arria 10
Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18 11:33:17 +02:00
Ley Foon Tan
2b09ea48dd arm: socfpga: Restructure reset manager driver
Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18 11:33:17 +02:00
Marek Vasut
f2f3782ead arm: socfpga: Define NAND reset bit
Define the NAND reset bit and fix the ordering of the macros.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-22 21:30:02 +01:00
Philipp Rosenberger
8a30e3a73a arm: socfpga: reset: FIX address of tstscratch register
The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset
of the tstscratch register ist 0x54 not 0x24.

Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02
page 3-17 Reset Manager Module Address Map

Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>
2015-11-30 13:30:19 +01:00
Dinh Nguyen
c624d07f3f arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-11-03 17:32:16 +01:00
Marek Vasut
34122eb262 arm: socfpga: reset: Add SDMMC, QSPI and DMA defines
Add SDMMC, QSPI and DMA reset defines. These are needed by SPL
so that we can boot from SD card and QSPI.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Marek Vasut
3191611a05 arm: socfpga: reset: Add function to reset add peripherals
Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Marek Vasut
a71df7aa4f arm: socfpga: reset: Replace ad-hoc reset functions
Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Marek Vasut
bdfc2ef64a arm: socfpga: reset: Implement unified function to toggle reset
Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Marek Vasut
1115cd2de7 arm: socfpga: reset: Start reworking the SoCFPGA reset manager
Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset in permodrstN register and which permodrstN register the
reset is located in from this abstract reset number. Use these
macros throughout the reset manager.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Marek Vasut
8d009e4542 arm: socfpga: reset: Add missing reset manager regs
Define two missing reset manager registers, which are in the
SoCFPGA CV datasheet.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Masahiro Yamada
30088b0997 ARM: socfpga: move SoC headers to mach-socfpga/include/mach
Move headers to mach-socfpga as well.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-07 05:21:15 +02:00
Renamed from arch/arm/include/asm/arch-socfpga/reset_manager.h (Browse further)