u-boot/arch/arm/mach-socfpga/include/mach/reset_manager.h
Marek Vasut 32f99757f4 ARM: socfpga: Repair A10 EMAC reset handling
The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18 10:30:46 +02:00

47 lines
1.4 KiB
C

/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
*/
#ifndef _RESET_MANAGER_H_
#define _RESET_MANAGER_H_
void reset_cpu(ulong addr);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
const u8 phymode));
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
/*
* Define a reset identifier, from which a permodrst bank ID
* and reset ID can be extracted using the subsequent macros
* RSTMGR_RESET() and RSTMGR_BANK().
*/
#define RSTMGR_BANK_OFFSET 8
#define RSTMGR_BANK_MASK 0x7
#define RSTMGR_RESET_OFFSET 0
#define RSTMGR_RESET_MASK 0x1f
#define RSTMGR_DEFINE(_bank, _offset) \
((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
/* Extract reset ID from the reset identifier. */
#define RSTMGR_RESET(_reset) \
(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
/* Extract bank ID from the reset identifier. */
#define RSTMGR_BANK(_reset) \
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
/* Create a human-readable reference to SoCFPGA reset. */
#define SOCFPGA_RESET(_name) RSTMGR_##_name
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include <asm/arch/reset_manager_gen5.h>
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#include <asm/arch/reset_manager_arria10.h>
#endif
#endif /* _RESET_MANAGER_H_ */