Commit graph

11998 commits

Author SHA1 Message Date
Alex Marginean
3499dd033c ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Vabhav Sharma
c1ead04bc4 arm64: lx2160a: dts: Fix UART node status
LX2160A PL011 UART driver fetch IP block values using
platform data from board file instead of device tree.

Modified UART nodes in device tree to disable state.

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Ran Wang
0cfa00cdb9 armv8: Add workaround for USB erratum A-050106
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Michael Walle
055aa33ff9 armv8: layerscape: fix SPL multi DTB loading
Mark board_fit_config_name_match() as weak so a board can overwrite the
empty function.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Simon Glass
bcee8d6764 dm: gpio: Allow control of GPIO uclass in SPL
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.

Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.

Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.

This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Suman Anna
1045ff4d1a ARM: DRA7: Fixup DSP OPP_HIGH clock rate on DRA76P/DRA77P SoCs
The commit 1b42ab3eda ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") added the core logic to update the kernel
device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on
a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx
family of SoCs.

The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though
provide a higher performance and can run at a higher clock frequency
of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the
correct clock rates on these SoCs. Note that this higher clock rate is
not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or
AM574x SoCs) that follow the ABZ package.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-12-09 14:00:24 -05:00
Tom Rini
ac1ca99926 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-net 2019-12-09 13:48:22 -05:00
Vignesh Raghavendra
4886f1cb59 arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT nodes
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Nevo Hed
06f555274e arm: dts: armada-cp110-*dtsi: add xmdio nodes
Based on upstream-linux
See https://github.com/torvalds/linux/commit/f66b2aff.

However made the XSMI register window 0x16 (22) bytes per my reading
of the functional spec.  Similar commits in Marvels own repo bump it
to 0x200 (512) bytes but I did not see the reasoning for that.

https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/4d932b4.

Also added device-name attributes to prevent ambiguity in the `mdio`
command.

Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Grygorii Strashko
5efb69298b arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to rgmii-rxid
The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Joe Hershberger
fb8977c5be net: Always build the string_to_enetaddr() helper
Part of the env cleanup moved this out of the environment code and into
the net code. However, this helper is sometimes needed even when the net
stack isn't included.

Move the helper to lib/net_utils.c like it's similarly-purposed
string_to_ip(). Also rename the moved function to similar naming.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reported-by: Ondrej Jirman <megous@megous.com>
2019-12-09 09:47:41 -06:00
Heinrich Schuchardt
0c5c3f2935 arm: -march=armv5t for ARM11
In GCC 9 support for the Armv5 and Armv5E architectures (which have no
known implementations) has been removed, cf.
https://gcc.gnu.org/gcc-9/changes.html

Commit 16540d07fd ("arm: fix -march for ARM11") changed the value of the
compiler flag from -march=armv5 and -march=armv5t into -march=armv6 for
ARM11.

The values prior to this patch were:

    arch-$(CONFIG_CPU_ARM1136)     =-march=armv5
    arch-$(CONFIG_CPU_ARM1176)     =-march=armv5t

The change lead to a regression with the Raspberry Pi Zero W not booting
anymore.

Use -march=armv5t both for ARM1136 and ARM1176.

Fixes: 16540d07fd ("arm: fix -march for ARM11")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Joris Offouga <offougajoris@gmail.com>
2019-12-09 10:36:00 -05:00
Tom Rini
2f02845817 Fixes for 2020.01
-----------------
 
 - imx8qxp_mek: increase buffer sizes and args number
 - Fixes for imx7ulp
 - imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
 - colibri_imx7: reserve DDR memory for Cortex-M4
 - vining2000: fixes and convert to ethernet DM
 - imx8m: fix rom version check to unbreak some B0 chips
 - tbs2910: Disable VxWorks image booting support
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Merge tag 'u-boot-imx-20191209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.01
-----------------

- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support
2019-12-09 10:32:08 -05:00
Patrick Wildt
6a4b07e086 imx8m: fix rom version check to unbreak some B0 chips
Recently the version check was improved to be able to determine that
we're running on SoC revision 2.1.  A check for B0 was tightened so
that it now must equal 0x20 instead of being bigger than 0x20.  On
some B0 chips the value returned is 0x1020 instead of 0x20.  This
means even though it's B0, the check will fail and code relying on
the correct chip revision will make wrong decisions.  There is no
documentation of those bits, but it seems that NXP always uses a
byte to encode the revision.  Thus remove the upper bits to fix the
regression.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
2019-12-09 11:52:06 +01:00
Tom Rini
bead4f2f2c Merge tag 'u-boot-rockchip-20191206' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rockchip pwm driver update to support all the SoCs
- RK3308 GMAC and pinctrl support
- More UART interface support on PX30 and pmugrf reg fix
- Fixup on misc for eth_addr/serial#
- Other updates on variant SoCs
2019-12-06 10:35:18 -05:00
Marek Vasut
edaec53212 ARM: imx: vining2000: Repair PCIe support
Ever since the conversion to DM PCI, the board was missing the PCIe DT
nodes, hence the PCI did not really work. Fill in the DT nodes and add
missing PCIe device reset.

Moreover, bring the PCIe power domain up before booting Linux. This is
mandatory to keep old broken vendor kernels working, as they do not do
so and depend on the bootloader to bring the power domain up.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-12-06 13:57:42 +01:00
Marek Vasut
7d84f4469f ARM: imx: vining2000: Convert to SPL framework
In preparation for use of DDR DRAM fine-tuning upon boot,
convert the board to SPL framework instead of using DCD
tables to bring up DRAM and pinmux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
2019-12-06 13:57:42 +01:00
Marek Vasut
df1b721f60 ARM: mx6: pmu: Expose PMU LDO configuration interface
Make the PMU LDO configuration interface available to board code,
so that board code can reconfigure the internal LDOs of the SoC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
2019-12-06 13:57:42 +01:00
Igor Opaniuk
c671d8af0b board: colibri_imx7: reserve DDR memory for Cortex-M4
i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for
the rpmsg communication. Both use cases need a fixed location of
memory reserved. For the rpmsg use case the reserved area needs
to be in sync with the kernel's hardcoded vring descriptor location.

Use the linux,usable-memory property to carve out 1MB of memory
in case the M4 core is running. Also make sure that the i.MX 7
specific rpmsg driver does not get loaded in case we do not carve
out memory.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-12-06 12:09:30 +01:00
Fabio Estevam
d396f1384c mx6: Allow configuring the NoC registers on i.MX6QP
The NoC registers on i.MX6QP needs to be configured, otherwise some
usecases in the kernel behave incorrectly, such as rotation and resize.

Currently the NoC registers are not configured in the kernel, so
configure them in U-Boot like it is done in the NXP U-Boot tree.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2019-12-06 12:09:25 +01:00
Fabio Estevam
2d4b87f867 mx7ulp: Sync the device tree related files
Sync the mx7ulp device tree related files with the one from
NXP U-Boot vendor tree (imx_v2019.04_4.19.35_1.0.0).

The mainline support for i.MX7ULP is very premature at this stage.

We should probably re-sync with mainline Linux dts when it gets
in better shape, but for now sync with the U-Boot vendor code.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
Fabio Estevam
d136eb9bfe mx7ulp: scg: Remove unnused scg_a7_apll_init()
scg_a7_apll_init() is not called anywhere, so remove such dead code

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
Fabio Estevam
0619af0942 mx7ulp: Remove the _RUN notation from the PMC1 LDOVL definitions
The LDOVL definitions is common to all the modes, not only RUN mode,
so in order to avoid confusion, remove the _RUN notation from the PMC1
LDOVL definitions.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
Fabio Estevam
b8cabb0e3d mx7ulp: Introduce the CONFIG_LDO_ENABLED_MODE option
Introduce the CONFIG_LDO_ENABLED_MODE option so that i.MX7ULP boards
designed to operate with LDO enabled mode can work with 0.95V at LDO
output in RUN mode as per the datasheet.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
Fabio Estevam
72a093a8ac mx7ulp: Print the LDO mode status
As per the i.MX7ULP datasheet, it can boot in LDO enabled mode
or LDO bypass mode.

Print the LDO mode status in the U-Boot log for convenience.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-12-06 12:05:08 +01:00
David Wu
e0e6c96a67 arm: rockchip: rk3308: Initialize the iomux configuration
When we want to use plus pinctrl feature, we need to enable
them at spl.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
David Wu
4ee6d51c5a pwm: rk_pwm: Make PWM driver to support all Rockchip Socs
This PWM driver can be used to support pwm functions
for on all Rockchip Socs.

The previous chips than RK3288 did not support polarity,
and register layout was different from the RK3288 PWM.

The RK3288 keep the current functions.

RK3328 and the chips after it, which can support hardware lock,
configure duty, period and polarity at next same period, to
prevent the intermediate temporary state.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
David Wu
aebd9eddb3 dts: rk3308: Enable ethernet function supported for Firefly ROC_RK3308_CC
The Firefly ROC_RK3308_CC use ref_clock of input mode,
and rmii pins of m1 group.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
David Wu
982fab393d arm: dts: Add mac node for rk3308 at dtsi level
The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
Heiko Stuebner
fd3a7ae8e6 rockchip: misc: protect serial# from getting overwritten
serial# is one of the vendor properties and thus protected from being
overwritten if already set. If env_set is called anyway this result in
some nasty warnings, so check for presence before trying that.

In the same direction check for the presence of cpuid# and compare it
to the actual hardware and emit a warning if they don't match.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Heiko Stuebner
d490fadc70 rockchip: misc: don't fail if eth_addr already set
rockchip_setup_macaddr() runs from an initcall, so returning an error
code will make that initcall fail thus breaking the boot process.

And if an ethernet address is already set this is definitly not a
cause for that, so just return success in that case.

Fixes: 0482538499 ("rockchip: rk3399: derive ethaddr from cpuid");
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Paul Kocialkowski
c541bfda2f rockchip: px30: Add support for using UART3 as debug UART
Some generic PX30 SoMs found in the wild use UART3 as their debug output
instead of UART2 (used for MMC) and UART5.

Make it possible to use UART3 as early debug output, with the associated
clock and pinmux configuration. Two sets of output pins are supported (M0/M1).

Future users should also note that the pinmux default in the dts is to use
the M1 pins while the Kconfig option takes M0 as a default.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
2019-12-05 23:53:07 +08:00
Paul Kocialkowski
ec4fafdf1f rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to CONFIG_DEBUG_UART_CHANNEL
UART3 also has two sets of pins that can be selected.

Rename the config option to a common name, to allow it to be used for both
UART2 and UART3.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Paul Kocialkowski
b0c5e37d0e rockchip: px30: Fixup PMUGRF registers layout order
According to the PX30 TRM, the iomux registers come first, before the pull
and strength control registers.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
2019-12-05 23:53:07 +08:00
Andy Yan
afe18f205e rockchip: px5: enable spl-fifo-mode for emmc for px5-evb
We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Andy Yan
081a51c937 rockchip: rk3308: enable spl-fifo-mode for emmc
We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.

And show my best respect to Heiko's work for this solution.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-05 23:53:07 +08:00
Thomas Hebb
9f67b56772 Fix typo in macros, "FIRMEWARE" -> "FIRMWARE"
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-12-05 10:28:39 -05:00
Miquel Raynal
eb446ef625 cmd: nand/sf: isolate legacy code
The 'sf' command is not supposed to rely on the MTD stack, but both
'sf' and 'nand' commands use helpers located in mtd_uboot.c. Despite
their location, these functions do not depend at all on the MTD
stack.

This file (drivers/mtd/mtd_uboot.c) is only compiled if CONFIG_MTD is
selected, which is inconsistent with the current situation. Solve this
by moving these three functions (which are only used by the above two
commands) out of mtd_uboot.c and put them in a C file only compiled
with cmd/sf.c and cmd/nand.c.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Don't export get_part function now]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-04 17:10:51 -05:00
Miquel Raynal
88718be300 mtd: rename CONFIG_NAND -> CONFIG_MTD_RAW_NAND
Add more clarity by changing the Kconfig entry name.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Re-run migration, update a few more cases]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2019-12-03 23:04:10 -05:00
mingming lee
abf2c68566 ARM: MediaTek: add basic support for MT8518 boards
This adds a general board file based on MT8518 SoCs from MediaTek.

Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.

This commit is adding the basic boot support for the MT8518 eMMC board.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
[trini: Migrate env location to defconfig, set ENV_IS_IN_MMC]
Signeed-off-by: Tom Rini <trini@konsulko.com>
2019-12-03 12:00:03 -05:00
mingming lee
485627dd5f pinctrl: add driver for MT8518
Add Pinctrl driver for MediaTek MT8518 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03 08:44:14 -05:00
mingming lee
13e89d7522 ARM: MediaTek: Add support for MediaTek MT8518 SoC
Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03 08:44:14 -05:00
Bartosz Golaszewski
598d9bccc5 board: omapl138_lcdk: add the mmc device to SPL
We don't have full device-tree support in SPL yet - add an appropriate
U_BOOT_DEVICE() to the board file.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-12-03 08:44:14 -05:00
Bartosz Golaszewski
6a97153cbf mmc: davinci: drop support for ti,dm6441-mmc
The DM family of DaVinci SoCs is no longer supported. Drop the
irrelevant code from the driver.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-12-03 08:44:13 -05:00
Giulio Benetti
1b3d24b735 armv7m: cache: add invalidate_icache_all() stub
This commit:
d409c96216
causes build failure with ICACHE enabled. This is due to missing
invalidate_icache_all() stub. Let's add empty invalidate_icache_all() in
the case where ICACHE is not enabled.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2019-12-03 08:43:24 -05:00
Thomas Hebb
32f2ca2a7e cosmetic: Fix spelling and whitespace errors
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-12-03 08:43:23 -05:00
Simon Glass
5255932f01 common: Move some board functions out of common.h
A number of board function belong in init.h with the others. Move them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:21 -05:00
Simon Glass
67c4e9f815 common: Move board_get_usable_ram_top() out of common.h
Move this function into init.h which seems to be designed for this sort
of thing. Also update the header to declare struct global_data so that it
can be included without global_data.h being needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:04 -05:00
Simon Glass
288b29e44d common: Move command functions out of common.h
Move these functions into the command.h header file which is a better fit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:02 -05:00
Simon Glass
36bf446b64 common: Move enable/disable_interrupts out of common.h
Move these two functions into the irq_funcs.h header file. Also move
interrupt_handler_t as this is used by the irq_install_handler() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:01 -05:00