Commit graph

86435 commits

Author SHA1 Message Date
Jonas Karlman
0030d49715 mmc: rockchip_sdhci: Remove unneeded emmc_phy_init
Remove the unneeded emmc_phy_init now that the no-inverter flag is
handled correctly after commit 2321a991bb ("rockchip: sdhci: rk3568:
bypass DLL when clk <= 52 MHz").

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
b8c394b726 mmc: rockchip_sdhci: Fix use of device private data
The device private data is misused in rockchip_sdhci_of_to_plat and
rockchip_sdhci_execute_tuning.

In these functions dev_get_priv is assigned to struct sdhci_host:

  struct sdhci_host *host = dev_get_priv(dev);

Instead, the sdhci host should refer to host in struct rockchip_sdhc:

  struct rockchip_sdhc *priv = dev_get_priv(dev);
  struct sdhci_host *host = &priv->host;

Because host is the first member in struct rockchip_sdhc this is not a
real problem, lets fix it anyway and also use priv name consistently.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
c1425ed8f8 mmc: sdhci: Set UHS Mode Select field for UHS SDR25 mode
Set correct UHS Mode Select field value for UHS SDR25 (50MHz) mode.

Fixes: d1c0a2200a ("mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
7774b79299 mmc: sdhci: Fix HISPD bit handling for MMC HS 52MHz mode
Set High Speed Enable bit for MMC High Speed (52MHz) mode.

Fixes: f12341a952 ("mmc: sdhci: Fix HISPD bit handling")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Chris Morgan
f89167bb74 ARM: dts: rockchip: rk3588s-u-boot: Add rng node
Add a node for the trng found on RK3588 SoCs.

Changes in V3:
 - Added Reviewed-By tag.

Changes in V2:
 - None

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2023-04-21 15:16:01 +08:00
Chris Morgan
5891282bf3 rockchip: rng: add trngv1 for rk3588
This adds support for the TRNG found in the RK3588 SoC to the
rockchip_rng driver so that it can be used for things such as
seeding randomness to Linux.

Changes in V3:
 - Moved notes from commit to cover letter.
 - Added Reviewed-By tag.

Changes in V2:
 - Modified Kconfig to note that the Rockchip RNG driver supports all
   versions of the hardware (v1, v2, and the trng in the rk3588).

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
45717d6efd clk: rockchip: rk3568: Add dummy I2S1_MCLKOUT_TX clock support
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock
in assigned-clocks, add dummy support to set parent of this clock to the
rk3568 cru driver.

Fixes probe of pmic driver and missing regulators on affected boards,
rk3568-evb and rk3568-rock-3a.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
518fa3441e pinctrl: rockchip: Fix IO mux selection on RK3568
IO mux selection is not working correctly for all pins. Sync mux route
data from linux to add any missing and update wrong trigger pins to fix
this. Also apply the pull-up fix needed for GPIO0 D3-D6.

Fixes: 1977d746aa ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21 15:16:01 +08:00
Jonas Karlman
58c23015c9 rockchip: rk3588: Sync sdmmc node from linux-next
Sync the sdmmc node from linux-next, include required nodes in SPL and
imply Kconfig options required for functional sdmmc clk in SPL and
U-Boot proper.

This make it possible for both SPL and U-Boot proper to configure sdmmc
clocks. In SPL, before TF-A is loaded, scru regs is configured, in
U-Boot proper a SCMI message is sent to TF-A.

Fixes: 95c8656b72 ("ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
6737771600 rockchip: rk3588: Add support for sdmmc clocks in SPL
Booting from sdmmc on RK3588 currently works because of a workaround in
the device tree, clocks are reordered so that the driver use ciu-sample
instead of ciu, and the BootRom initializes sdmmc clocks before SPL is
loaded into DRAM.

The sdmmc clocks are normally controlled by TF-A using SCMI. However,
there is a need to control these clocks in SPL, before TF-A has started.

This adds a rk3588_scru driver to control the sdmmc clocks in SPL before
TF-A has started, using scru regs. It also adds a small glue driver to
bind the scmi clock node to the rk3588_scru driver in SPL.

Fixes: 7a474df740 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
2229758118 clk: scmi: Add Kconfig option for SPL
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options
enabled and SPL_FIRMWARE disabled result in the following error.

  drivers/clk/clk_scmi.o: in function `scmi_clk_gate':
  drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg'
  drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno'
  drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate':
  drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg'
  drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno'
  drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate':
  drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg'
  drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno'
  drivers/clk/clk_scmi.o: in function `scmi_clk_probe':
  drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel'
  make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
  make: *** [Makefile:2043: spl/u-boot-spl] Error 2

Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
e1962a9efe rockchip: rk35xx: Enable fdtoverlay and kernel compression
Add fdtoverlay_addr_r, kernel_comp_addr_r and imply use of
OF_LIBFDT_OVERLAY on RK3568 and RK3588 to support fdtoverlay
and kernel compression.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-21 15:16:01 +08:00
Jonas Karlman
9f412347be rockchip: rk35xx: Fix boot with a large fdt blob
The TF-A blobs used to boot RK3568 and RK3588 boards is based on atf
v2.3. Mainline atf v2.3 contains an issue that could lead to a crash
when it fails to parse the fdt blob being passed as the platform param.
An issue that was fixed in atf v2.4.

The vendor TF-A seem to suffer from a similar issue, and this prevents
booting when fdt blob is large enough to trigger this condition.

Fix this by implying SPL_ATF_NO_PLATFORM_PARAM to let u-boot pass a
NULL pointer instead of the fdt blob as the platform param.

This fixes booting Radxa ROCK 3A after recent sync of device tree.

Fixes: 073d911ae6 ("rockchip: rk3568-rock-3a: Sync device tree from linux")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21 15:16:01 +08:00
Jonas Karlman
f1e190a192 rockchip: rk3588-rock-5b: Fix sdmmc boot
Running U-Boot from a SD-card on ROCK 5 Model B fails to load atf using
DMA and prints debug_uart messages.

  <debug_uart>

  <debug_uart>

  U-Boot SPL 2023.04-rc3 (Mar 12 2023 - 00:30:16 +0000)
  Trying to boot from MMC1
  ## Checking hash(es) for config config-1 ... OK
  ## Checking hash(es) for Image atf-1 ... sha256 error!
  Bad hash value for 'hash' hash node in 'atf-1' image node
  mmc_load_image_raw_sector: mmc block read error
  SPL: failed to boot from all boot devices
  ### ERROR ### Please RESET the board ###

Use fifo-mode to disable DMA in SPL, add same-as-spl to boot-order and
remove DEBUG_UART_ANNOUNCE option to fix this.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
John Keeping
9fea3696ef rockchip: otp: fix misc_read() return values
The documentation for misc_read() says:

    Return: number of bytes read if OK (may be 0 if EOF), -ve on error

The Rockchip efuse driver implements this so it should return the number
of bytes read rather than zero on success.  Fix this so that the driver
follows the usual contract for read operations.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
John Keeping
a48d13535a rockchip: efuse: fix misc_read() return values
The documentation for misc_read() says:

    Return: number of bytes read if OK (may be 0 if EOF), -ve on error

The Rockchip efuse driver implements this so it should return the number
of bytes read rather than zero on success.  Fix this so that the driver
follows the usual contract for read operations.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
John Keeping
999680c4ed rockchip: misc: fix misc_read() return check
misc_read() is documented to return the number of bytes read or a
negative error value.  The Rockchip drivers currently do not implement
this correctly and instead return zero on success or a negative error
value.

In preparation for fixing the drivers, fix the condition here to only
error on negative values.

Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Chris Morgan
6fa83833b0 rockchip: video: Add support for RK3568 DSI Host
Add support for DSI Host controller on Rockchip RK3568. This driver
is heavily based on the Rockchip dw_mipi_dsi_rockchip.c driver in
Linux and the stm32_dsi.c driver in U-Boot. It should be easy to add
support for other SoCs as the only missing component from the mainline
driver is setting the VOP big or VOP little (which the rk3568 does
not have).

Driver was tested for use in sending commands to a DSI panel in order
to obtain the panel ID.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Chris Morgan
bf57dd5889 drivers: phy: add Innosilicon DSI-DPHY driver
Add support for the Innosilicon DSI-DPHY driver for Rockchip SOCs.
The driver was ported from Linux and tested on a Rockchip RK3566
based device to query the panel ID via a DSI command.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonathan Liu
cf8b415d5c ram: rk3399: add missing high row detection
For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin
prints:
"Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB"

U-Boot TPL prints:
"BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB"

Add missing high row detection so that U-Boot TPL prints Row=16, same as
the Rockchip ddr init bin:
"BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB"

Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Jonas Karlman
88b962f393 gpio: rockchip: Add support for RK3568 and RK3588 banks
The GPIO V2 controller on RK3568 and RK3588 works very similar to
prior generation, main difference is the use of a write mask in the
upper 16 bits and register address offset have changed.

GPIO_VER_ID is a new register at 0x0078 that is used to determine when
the driver should use new or old register offsets and values. Earlier
generation return 0x0 from this offset.

Refactor code and add support for the GPIO V2 controller used in RK3568
and RK3588.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
df2af4083c rockchip: configs: mk808: enable usb support
Enable usb support in the mk808_defconfig.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
f1088af574 rockchip: configs: mk808: change CONFIG_TPL_TEXT_BASE
Currently the Rockchip rk3066a u-boot-tpl.bin file needs
to add the characters "RK30", while the other SoCs replace
the first 4 bytes. Bring this in line with the rest by
lowering CONFIG_TPL_TEXT_BASE and update rockchip.rst
instructions.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
98125086d6 arm: dts: rockchip: sync rk3066/rk3188 DT files from linux-next v6.2-rc4
Sync rk3066/rk3188 DT files from Linux.
This is the state as of linux-next v6.2-rc4.
New nfc node for MK808 rk3066a.
CRU nodes now have a clock property.
To prefend dtoc errors a fixed clock must also be
included for tpl/spl in the rk3xxx-u-boot.dtsi file.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
e16be4dd8b arm: dts: rockchip: rk3188-u-boot: add gpio-ranges
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3188-u-boot.dtsi
for now till a better method is found.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
fed814c088 arm: dts: rockchip: rk3066a-u-boot: add gpio-ranges
The gpio node names are made generic, but without
gpio bank ID. Add gpio-ranges to rk3066a-u-boot.dtsi
for now till a better method is found.
Disable gpio6 as the driver gives an error code
on return as status.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
3c4549771d rockchip: gpio: rk_gpio: use ROCKCHIP_GPIOS_PER_BANK as divider
The current divider to calculate the bank ID can change.
Given the Rockchip TRM not all gpio-banks have 32 pins per bank.
The "gpio-ranges" syntax allows multiple items with variable number
of pins. Use a constant ROCKCHIP_GPIOS_PER_BANK as fixed divider.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
ba607e2b9a arm: dts: rockchip: rk3288: partial sync pwm nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the pwm nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
2c2d782556 clk: rockchip: clk_rk3288: add PCLK_RKPWM
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM
instead of PCLK_PWM. They have the same pclk_cpu parent,
so add PCLK_RKPWM to rk3288_clk_get_rate().

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
7c1ee7a848 arm: dts: rockchip: rk3288: partial sync vop/lvds/mipi/hdmi nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the vop/lvds/mipi/hdmi nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
bf13676e0b arm: dts: rockchip: rk3288: partial sync edp node
The rk3288 edp node has a phy node in Linux with a clock
property while current U-Boot driver expects this clock
on position index 1. Move U-Boot-specific DT clock properties
to rk3288-u-boot.dtsi and partially sync the edp node.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:01 +08:00
Johan Jonker
e2b57ffbaf video: rockchip: rk_vop: add rk3288-dp compare string
In the current rk3288.dtsi file the compatible string for
the DisplayPort(DP) node ends with "edp". The string in the
binding ends with "dp" which conflicts with "cdn-dp" as a
search term. Add "rk3288-dp" as compare string to select
vop_id.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Johan Jonker
da5ae37fcd arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
In order to better compare the Linux rk3288.dtsi
version 6.3 -rc2 with the U-Boot version partial
sync the grf and pmu nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Johan Jonker
35e9e8aebf arm: dts: rockchip: rk3288: move io-domains nodes
In order to better compare the Linux rk3288.dtsi version
with the U-Boot version move the io-domains nodes.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>  # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Jianqun Xu
4f51064533 pinctrl: rockchip: support rk3588 pinctrl
Add support for Rockchip rk3588 variant of pinctrl.

The driver is adapted from the Linux driver.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[eugen.hristev@collabora.com:
port to latest U-boot, bring more changes from Linux
use translated pull values table]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21 15:16:00 +08:00
John Keeping
24fea3f837 rockchip: rk3288: Use ft_system_setup instead of ft_board_setup
ft_board_setup() should be availble for use in board files but using it
in the rk3288 machine file blocks this functionality.

ft_system_setup() is the more appropriate function to use in a machine
definition.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Jonas Karlman
f7ad2912c6 rockchip: Use an external TPL binary on RK3588
There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL
and instead an external TPL binary must be used to generate a bootable
u-boot-rockchip.bin image.

Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for
RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
2023-04-21 15:16:00 +08:00
Kever Yang
cf8658cdac board: rockchip: Add rk3588 evb
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for
rockchip and also a reference board for board vendors.

Hardware:
SoC: RK3588
DRAM: LPDDR4X 8GB
Debug: UART2 via USB
PCIe: 3x4 *1
SATA *2
HDMI out *2
HDMI IN *1
USB2.0 Host *2
USB3.0 Host *1
Type C *1
MIPI DSI panel

dts Sync from Linux v6.2.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@edgeble.ai>
2023-04-21 15:16:00 +08:00
Quentin Schulz
c3328c3ba8 rockchip: ringneck-px30: enforce ENV_IS_NOWHERE with Kconfig select
Instead of letting the compiler error out if CONFIG_ENV_IS_NOWHERE is
not selected by the user, let's just enforce it when the user builds for
Ringneck PX30 so that no check needs to be performed by the compiler and
the configuration is always valid.

Suggested-by: Tom Rini <trini@konsulko.com>
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Quentin Schulz
6a89465f3f rockchip: puma-rk3399: enforce ENV_IS_NOWHERE with Kconfig select
Instead of letting the compiler error out if CONFIG_ENV_IS_NOWHERE is
not selected by the user, let's just enforce it when the user builds for
Puma RK3399 so that no check needs to be performed by the compiler and
the configuration is always valid.

Suggested-by: Tom Rini <trini@konsulko.com>
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Vasily Khoruzhick
7786710adb rockchip: sdhci: rk3568: fix clock setting logic
mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.

Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.

Fix it by using MAX(mmc->tran_speed, mmc->clock)

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21 15:16:00 +08:00
Ilias Apalodimas
b10bfd0019 efi_loader: Fix flexible array member definitions
When a structure contains a flexible array member, it is not supposed to be
included in arrays or other structs.
Quoting the C spec [0]
"Such a structure (and any union containing, possibly recursively, a
member that is such a structure) shall not be a member of a structure
or an element of an array."

IOW efi_hii_keyboard_layout should not include
struct efi_key_descriptor descriptors[]; since we use it at the
declaration of struct efi_hii_keyboard_package.

[0] https://www.dii.uchile.cl/~daespino/files/Iso_C_1999_definition.pdf
chapter 6.7.2.1

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-21 08:50:35 +02:00
Heinrich Schuchardt
9031cb627c test: fix launch_efi()
We cannot use old_dtb in the finally block if it has not been assigned
before the try block.

test/py/tests/test_efi_fit.py:458:30:
E0601: Using variable 'old_dtb' before assignment (used-before-assignment)

Fixes: 8391f95549 ("test/py: Create a test for launching UEFI binaries from FIT images")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-21 08:50:35 +02:00
Heinrich Schuchardt
e2a0a07ed0 sandbox: enable CONFIG_EFI_CAPSULE_AUTHENTICATE
Without CONFIG_EFI_CAPSULE_AUTHENTICATE=y the following tests are skipped:

* test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
* test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-21 08:50:35 +02:00
Heinrich Schuchardt
b54477ff8b test: fix pylint warning for capsule tests
Fix pylint warnings like:

* Class inherits from object
* Missing module description
* Missing class description
* First line of comment blank
* Superfluous imports

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-21 08:50:35 +02:00
Heinrich Schuchardt
4bccbd32fb efi_loader: remove unused efi_capsule_authenticate
Remove an unused implementation of efi_capsule_authenticate().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-21 08:50:35 +02:00
Heinrich Schuchardt
8626ef32e9 doc: codingstyle: Python coding style
Indicate that we follow PEP8 and PEP257.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-21 08:50:35 +02:00
Samuel Holland
04d16be554 riscv: Support CONFIG_REMAKE_ELF
Add flags to tell objcopy what kind of ELF to create.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-04-20 20:45:08 +08:00
Bin Meng
9a6569a043 riscv: Update alignment for some sections in linker scripts
Some sections in the linker scripts are aligned to 4 bytes, which
may cause misaligned exception on some platforms, e.g.: clearing
the bss section on 64-bit hardware if __bss_start does not start
from a naturally 8 bytes aligned address.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20 20:45:08 +08:00
Bin Meng
3f37baae83 riscv: spl: Remove relocation sections
U-Boot SPL is not relocable. Drop these relocation sections.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20 20:45:08 +08:00