Fastest read command code look for fastest read command
taking inputs from spi->mode_rx and flags from param table
and controller mode_rx is always been a priority.
Since mode_rx is always set from controller side this optimized
code doesn't require much and this code required exctra overhead like
1) Maintain e_rx_cmd in param table
2) Maintain mode_rx in spi_slave {}
Hence removed this code, and look for read command from normal
spi->mode from spi_slave{} and params->flags
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
This udelay() was added as an HACK and is no longer required. All
read/write/erase operations work fine even without this delay. Hence,
remove the udelay() call.
Tested read/write/erase operation on AM437x SK. Also tested QSPI Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
TI QSPI has four 32 bit data registers which can be used to transfer 16
bytes of data at once. The register group QSPI_SPI_DATA_REG_3,
QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is
treated as a single 128-bit word for shifting data in and out. The bit
at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out
in case of 128 bit transfer mode. Therefore the first byte to be written
to flash should be at QSPI_SPI_DATA_REG_3[31-25] position.
Instead of writing 1 byte at a time when interacting with SPI NOR flash,
make use of all the four registers so that 16 bytes can be transferred
in one go.
With this patch, the flash write speed increases from ~250KBs/ to
~650KB/s on DRA74 EVM.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
During spi transfer, for example:
sspi 1:1.0 8 ff
the rx_len values will be:
rx_len = 0
rx_len = 4294967295
This caused a busy looping during xfer, this patch fixes it
by adding a check while reading the rx fifo
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on multiple CPUs simultaneously, which causes all sorts of
issues as the multiple instances of U-Boot clobber each other.
Prevent this from happening by simply hanging with an infinite loop if
we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum
as appropriate, is non-zero.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
The relocate_code function was handling cache maintenance incorrectly.
It copied U-Boot to its new location, flushed the caches & then
proceeded to apply relocations & jump to the new code without flushing
the caches again. This is problematic as the instruction cache could
potentially have already fetched instructions that hadn't had relocs
applied.
Rework this to perform the flush_cache call using the code in the
original copy of U-Boot, after having applied relocations to the new
copy of U-Boot. The new U-Boot can then be jumped to safely once that
cache flush has been performed.
As part of this, since the old U-Boot is used up until after that cache
flush, complexity around loading values from the GOT using a jump & link
instruction & loads from a table is removed. Instead we can simply load
the needed values with PTR_LA fromt the original GOT.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older MIPS Malta board.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Provide a trivial syscon driver matching the generic "syscon" compatible
string, allowing for simple system controllers to be used without a
custom driver just as in Linux.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Device model drivers have previously been matched to FDT nodes by virtue
of being the first driver in the driver list to be compatible with the
node. This ignores the fact that compatible strings in the device tree
are listed in order of priority - that is, if we have a node with 2
compatible strings & a driver that matches each then we should always
probe the driver that matches the first compatible string.
Fix this by looping through the compatible strings for a node when
attempting to bind it in lists_bind_fdt and checking each driver for
a match of the first string, then each driver for a match of the second
string etc. Effectively this inverts the loops over compatible strings &
drivers.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
The regmap_read & regmap_write functions were previously declared in
regmap.h but not implemented anywhere. The regmap implementation &
commit message of 6f98b7504f ("dm: Add support for register maps
(regmap)") indicate that only memory mapped accesses are supported for
now, so providing simple implementations of regmap_read & regmap_write
is trivial. The access size is presumed to be 4 bytes & endianness is
presumed native, which are the defaults for the regmap code in Linux.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The pch_gbe driver previously casted pointers to & from unsigned 32 bit
integers in many locations. This breaks the driver on 64 bit systems,
producing streams of compiler warnings about mismatched pointer &
integer sizes and then failing to keep track of addresses correctly at
runtime.
Fix the driver for 64 bit systems by using unsigned longs in place of
the previously used 32 bit integers.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reading the PCI BAR & converting the result to a physical address is not
safe across all architectures. For example on MIPS the virtual:physical
mapping is not 1:1, so we cannot directly make use of the physical
address.
Use the more generic BAR-mapping function dm_pci_map_bar to discover the
MMIO base address, which should work across architectures.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In pci_uclass_pre_probe an attempt is made to detect whether the parent
of a device is a PCI device and that the device is thus a bridge. This
was being done by checking whether the parent of the device is of the
UCLASS_ROOT class. This causes problems if the PCI controller is a child
of some other non-PCI node, for example a simple-bus node.
For example, if the device tree contains something like the following
then pci_uclass_pre_probe would incorrectly believe that the PCI
controller is a bridge, with a PCI parent:
/ {
some_child {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <>;
pci_controller: pci@10000000 {
compatible = "my-pci-controller";
device_type = "pci";
reg = <0x10000000 0x2000000>;
};
};
};
Avoid this incorrect detection of bridges by instead checking whether
the parent devices class is UCLASS_PCI and treating a device as a bridge
when this is true, making use of device_is_on_pci_bus to perform this
test.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Import a copy of the dt-bindings/interrupt-controller/mips-gic.h header
from Linux, such that we can use device trees which include it without
modification.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Previously ns16550 compatible UARTs probed via device tree have needed
their device tree nodes to contain a clock-frequency property. An
alternative to this commonly used with Linux is to reference a clock via
a phandle. This patch allows U-Boot to support that, retrieving the
clock frequency by probing the appropriate clock device.
For example, a system might choose to provide the UART base clock as a
reference to a clock common to multiple devices:
sys_clk: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <10000000>;
};
uart0: uart@10000000 {
compatible = "ns16550a";
reg = <0x10000000 0x1000>;
clocks = <&sys_clk>;
};
uart1: uart@10000000 {
compatible = "ns16550a";
reg = <0x10001000 0x1000>;
clocks = <&sys_clk>;
};
This removes the need for the frequency information to be duplicated in
multiple nodes and allows the device tree to be more descriptive of the
system.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The implementations of clk_get_by_index & clk_get_by_name are only
available when CONFIG_CLK is enabled. Provide the dummies when this is
not the case in order to avoid build failures.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Ensure that cache operations complete before returning from
mips_cache_reset by placing a completion barrier (sync instruction)
before the return. Without this there is no guarantee that the cache ops
will complete before any subsequent memory accesses, since they are
indexed cache ops & thus not implicitly ordered with memory accesses.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
During boot we set Config.K0=2 (uncached) such that any accesses to the
kseg0 memory region are performed uncached before the caches are
initialised. This write to the Config register introduces an execution
hazard between it & any following memory accesses (such as the load of
_gp), which we need to clear in order to ensure those memory accesses
are actually performed uncached. Clear this execution hazard with the
insertion of an ehb execution hazard barrier instruction.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, join the coherent domain after completing cache
initialisation.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Define names for registers holding cache sizes throughout
mips_cache_reset, in order to make the code easier to read & allow for
changing register assignments more easily.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
perform cache initialisation prior to lowlevel_init & DDR
initialisation. This allows for DDR initialisation code to run cached &
thus significantly faster.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS architecture.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Rather than probing the cache line sizes on every call of any cache
maintenance function, probe them once during boot & store the values in
the global data structure for later use. This will reduce the overhead
of the cache maintenance functions, which isn't a big deal yet but
becomes more important once L2 caches which may expose their properties
via coprocessor 2 or the CM are supported.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
In order to prepare for MIPS arch code making use of arch_cpu_init in a
later patch, stop using it from ath79 SoC code & instead use the new
mach_cpu_init which is provided for this purpose.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Currently we have a mismash of architectures which use arch_cpu_init
from architecture-wide code (arc, avr32, blackfin, mips, nios2, xtensa)
and architectures which use arch_cpu_init from machine/SoC level code
(arm, x86).
In order to clean this mess up & allow for both use cases, introduce a
new mach_cpu_init callback which is run immediately after arch_cpu_init.
This will allow for architectures to have arch-wide code without needing
individual machines to all implement their own arch_cpu_init with a call
to some common function.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
MIPSfpga is an FPGA based dev platform.
In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks
The FPGA dev board used is the Nexys4DDR board by Digilent.
For more information, check the Readme file in board/imgtec/xilfpga
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Mostly the same as the Kernel upstream device tree file except for
- alias for the serial console node
- ethernet node as the ethernet stuff isn't upstream on kernel.org yet
- uart clock-frequency passed directly in the node
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
out_be32 and in_be32 are actually #defined to little endian
writel/readl in arch/microblaze.
Just use __raw_writel/readl instead. That is also what is used
in the Linux kernel driver for this IP block
Tested on MIPSfpga. Can tftp a kernel.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Virtual to physical mapping isn't necessarily 1:1 for all architectures
Using ioremap_nocache allows for the arch code to translate the
physical address to a virtual address.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When DTO interrupt occurred, there are any remaining data still in FIFO
due to RX FIFO threshold is larger than remaining data. It also
causes that dwmmc didn't trigger RXDR interrupt, so is TX.
It's responsibility of driver to read remaining bytes on seeing DTO
interrupt.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
There are a few boards that use CONFIG_ISO_STRING as part of a sanity
check during firmware update at run time. Move this string to Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Convert CONFIG_MIP405T from SYS_EXTRA_OPTIONS to a real config
There are two boards, MIP405 and MIP405T that have a few differences.
Start by checking for CONFIG_TARGET_MIP405. Then introduce
CONFIG_TARGET_MIP405T and use that not CONFIG_MIP405T. Next, convert
also convert the usage of CONFIG_ISO_STRING to be based on Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Move the config IDENT_STRING to Kconfig and migrate all boards
[sivadur: Migrate zynq boards]
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[trini: Update configs, add some default to sunxi Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
To SD, there is no erase group, then the value erase_grp_size
will be default 1. When erasing SD blocks, the blocks will be
erased one by one, which is time consuming.
We use AU_SIZE as a group to speed up the erasing.
Erasing 4MB with a SD2.0 Card with AU_SIZE 4MB.
`time mmc erase 0x100000 0x2000`
time: 44.856 seconds (before optimization)
time: 0.335 seconds (after optimization)
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stephen Warren <swarren@nvidia.com>
Add function to read SD_STATUS information.
According to the information, get erase_timeout/erase_size/erase_offset.
Add a structure sd_ssr to include the erase related information.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stephen Warren <swarren@nvidia.com>
No need for per-SoC adjustment for this parameter. It should be
determined by the slowest hardware. Currently, no board overrides
this CONFIG, so 3.2 sec is large enough. (If not, we can make it
even larger.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This CONFIG is not configurable since it is not guarded by #ifndef.
Nobody has complained about that, so there is no need to keep it as
a CONFIG option.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
