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PowerPC: Update MIP405/MIP405T to use Kconfig better

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Convert CONFIG_MIP405T from SYS_EXTRA_OPTIONS to a real config

There are two boards, MIP405 and MIP405T that have a few differences.
Start by checking for CONFIG_TARGET_MIP405.  Then introduce
CONFIG_TARGET_MIP405T and use that not CONFIG_MIP405T.  Next, convert
also convert the usage of CONFIG_ISO_STRING to be based on Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2016-09-19 21:55:34 -04:00
parent a4d88920e5
commit adf32adb70
12 changed files with 36 additions and 45 deletions
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6
arch/powerpc/cpu/ppc4xx/4xx_pci.c
View file

@ -118,7 +118,8 @@ void pci_405gp_init(struct pci_controller *hose)
#endif
unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
|| defined(CONFIG_TARGET_MIP405T)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
@ -408,7 +409,8 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
#if !(defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
|| defined(CONFIG_TARGET_MIP405T))
/*
*As is these functs get called out of flash Not a horrible

3
arch/powerpc/cpu/ppc4xx/Kconfig
View file

@ -104,6 +104,9 @@ config TARGET_ICON
config TARGET_MIP405
bool "Support MIP405"
config TARGET_MIP405T
bool "Support MIP405T"
config TARGET_PIP405
bool "Support PIP405"

3
arch/powerpc/cpu/ppc4xx/resetvec.S
View file

@ -4,7 +4,8 @@
#if defined(CONFIG_440)
b _start_440
#else
#if defined(CONFIG_BOOT_PCI) && defined(CONFIG_MIP405)
#if defined(CONFIG_BOOT_PCI) && (defined(CONFIG_TARGET_MIP405) \
|| defined(CONFIG_TARGET_MIP405T))
b _start_pci
#else
b _start

16
board/mpl/common/common_util.c
View file

@ -20,7 +20,7 @@
#include "../pip405/pip405.h"
#include <asm/4xx_pci.h>
#endif
#ifdef CONFIG_MIP405
#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
#include "../mip405/mip405.h"
#include <asm/4xx_pci.h>
#endif
@ -36,7 +36,8 @@ extern int mem_test(ulong start, ulong ramsize, int quiet);
#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN /* ugly, but it works for now */
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
|| defined(CONFIG_TARGET_MIP405T)
/*-----------------------------------------------------------------------
* On PIP/MIP405 we have 3 (4) possible boot mode
*
@ -116,7 +117,7 @@ void setup_cs_reloc(void)
mtdcr(EBC0_CFGDATA, FLASH_CR_B);
}
}
#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) */
#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) */
#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
/* adjust flash start and protection info */
@ -190,12 +191,11 @@ mpl_prg(uchar *src, ulong size)
#if defined(CONFIG_PATI)
int start_sect;
#endif
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
|| defined(CONFIG_TARGET_MIP405T) || defined(CONFIG_PATI)
char *copystr = (char *)src;
ulong *magic = (ulong *)src;
#endif
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
if (uimage_to_cpu (magic[0]) != IH_MAGIC) {
puts("Bad Magic number\n");
return -1;
@ -241,7 +241,7 @@ mpl_prg(uchar *src, ulong size)
return (1);
}
#else /* #if !defined(CONFIG_PATI */
#else /* #if !defined(CONFIG_PATI) */
start = FIRM_START;
start_sect = -1;
@ -701,7 +701,7 @@ void video_get_info_str (int line_number, char *info)
strcpy(buf,"### No HW ID - assuming PIP405");
}
#endif
#ifdef CONFIG_MIP405
#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
if (!s || strncmp (s, "MIP405", 6)) {
strcpy(buf,"### No HW ID - assuming MIP405");
}

2
board/mpl/common/common_util.h
View file

@ -17,12 +17,10 @@ extern flash_info_t flash_info[]; /* info for FLASH chips */
void get_backup_values(backup_t *buf);
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
#define BOOT_MPS 0x01
#define BOOT_PCI 0x02
int get_boot_mode(void);
void setup_cs_reloc(void);
#endif
void check_env(void);
#if defined(CONFIG_CMD_DOC)

4
board/mpl/common/pci_parts.h
View file

@ -91,7 +91,7 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
{PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
{PCI_COMMAND, 0x0001, 2}, /* enable IO access */
#if !defined(CONFIG_MIP405T)
#if !defined(CONFIG_TARGET_MIP405T)
{PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
#else
{PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */
@ -101,7 +101,7 @@ static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
/* PIIX4 USB Controller Function 2 */
static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
#if !defined(CONFIG_MIP405T)
#if !defined(CONFIG_TARGET_MIP405T)
{PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
{PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */
{PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */

7
board/mpl/mip405/Kconfig
View file

@ -1,4 +1,4 @@
if TARGET_MIP405
if TARGET_MIP405 || TARGET_MIP405T
config SYS_BOARD
default "mip405"
@ -9,4 +9,9 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "MIP405"
config ISO_STRING
string
default "MEV-10082-001" if TARGET_MIP405T
default "MEV-10072-001" if TARGET_MIP405
endif

14
board/mpl/mip405/mip405.c
View file

@ -92,7 +92,7 @@ typedef struct {
unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
unsigned char ecc; /* if true, ecc is enabled */
} sdram_t;
#if defined(CONFIG_MIP405T)
#if defined(CONFIG_TARGET_MIP405T)
const sdram_t sdram_table[] = {
{ 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
3, /* Case Latenty = 3 */
@ -168,7 +168,7 @@ const sdram_t sdram_table[] = {
0xff,
0xff }
};
#endif /*CONFIG_MIP405T */
#endif /*CONFIG_TARGET_MIP405T */
void SDRAM_err (const char *s)
{
#ifndef SDRAM_DEBUG
@ -262,7 +262,7 @@ int init_sdram (void)
#endif
/* check board */
bc = in8 (PLD_PART_REG);
#if defined(CONFIG_MIP405T)
#if defined(CONFIG_TARGET_MIP405T)
if((bc & 0x80)==0)
SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
#else
@ -543,7 +543,7 @@ void ide_set_reset (int idereset)
void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
{
#if !defined(CONFIG_MIP405T)
#if !defined(CONFIG_TARGET_MIP405T)
unsigned char bc,rc,tmp;
int i;
@ -575,7 +575,7 @@ void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
* Check Board Identity:
*/
/* serial String: "MIP405_1000" OR "MIP405T_1000" */
#if !defined(CONFIG_MIP405T)
#if !defined(CONFIG_TARGET_MIP405T)
#define BOARD_NAME "MIP405"
#else
#define BOARD_NAME "MIP405T"
@ -777,7 +777,7 @@ void print_mip405_info (void)
(cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
#if !defined(CONFIG_MIP405T)
#if !defined(CONFIG_TARGET_MIP405T)
printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
@ -793,7 +793,7 @@ void print_mip405_info (void)
printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
printf ("IRQs:\n");
printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
#if !defined(CONFIG_MIP405T)
#if !defined(CONFIG_TARGET_MIP405T)
printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
#endif

2
board/mpl/pati/pati.h
View file

@ -201,7 +201,7 @@
#define PCI_VENDOR_ID_MPL 0x18E6
#define PCI_DEVICE_ID_PATI 0x00DA
#if defined(CONFIG_MIP405)
#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
#define PATI_FIRMWARE_START_OFFSET 0x00300000
#define PATI_ISO_STRING "MEV-10084-001"
#endif

3
configs/MIP405T_defconfig
View file

@ -1,8 +1,7 @@
CONFIG_PPC=y
CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10082-001 released"
CONFIG_4xx=y
CONFIG_TARGET_MIP405=y
CONFIG_SYS_EXTRA_OPTIONS="MIP405T"
CONFIG_TARGET_MIP405T=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y

19
include/configs/MIP405.h
View file

@ -17,7 +17,6 @@
* (easy to change)
***********************************************************/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_MIP405 1 /* ...on a MIP405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
@ -57,9 +56,6 @@
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP
#if !defined(CONFIG_MIP405T)
#endif
/**************************************************************
* I2C Stuff:
* the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
@ -312,7 +308,7 @@
/************************************************************
* IDE/ATA stuff
************************************************************/
#if defined(CONFIG_MIP405T)
#if defined(CONFIG_TARGET_MIP405T)
#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
#else
#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
@ -358,7 +354,7 @@
/************************************************************
* USB support EXPERIMENTAL
************************************************************/
#if !defined(CONFIG_MIP405T)
#if !defined(CONFIG_TARGET_MIP405T)
#define CONFIG_USB_UHCI
#define CONFIG_USB_KEYBOARD
@ -377,15 +373,4 @@
************************************************************/
#define CONFIG_BZIP2 1
/************************************************************
* Ident
************************************************************/
#define VERSION_TAG "released"
#if !defined(CONFIG_MIP405T)
#define CONFIG_ISO_STRING "MEV-10072-001"
#else
#define CONFIG_ISO_STRING "MEV-10082-001"
#endif
#endif /* __CONFIG_H */

2
scripts/config_whitelist.txt
View file

@ -3086,8 +3086,6 @@ CONFIG_MII_DEFAULT_TSEC
CONFIG_MII_INIT
CONFIG_MII_SUPPRESS_PREAMBLE
CONFIG_MINIFAP
CONFIG_MIP405
CONFIG_MIP405T
CONFIG_MIPS_HUGE_TLB_SUPPORT
CONFIG_MIPS_MT_FPAFF
CONFIG_MIRQ_EN