Commit graph

3 commits

Author SHA1 Message Date
James Doublesin
34f27b2e86 ram: k3-am654: Do not rely on default values for certain DDR register
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.

Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
Lokesh Vutla
355be915ed arm: dts: k3-am654: Update power-domains property for each node
Update the power-domain-cells to 2 and add the permissions
to each node. Mark the following nodes accessed by r5 as shared:
- DDR node
- main uart 0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-26 21:49:23 -04:00
Lokesh Vutla
00b34e9937 armv7r: dts: am654: Add initial support
Add R5 specific dts for am654-evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-16 16:51:59 -05:00