Commit graph

10 commits

Author SHA1 Message Date
Priyanka Jain
4909b89ec7 armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Ashish Kumar
6d9b82d085 armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
York Sun
4a3ab19322 armv8: ls2080a: Drop macro CONFIG_LS2080A
Use CONFIG_ARCH_LS2080A instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17 09:03:30 -07:00
York Sun
3c1d218a1d armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2016-04-06 10:26:46 -07:00
Prabhakar Kushwaha
06b5301043 armv8: ls2085a: Add support of LS2085A SoC
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:10:47 -08:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Prabhakar Kushwaha
e60476a01e board/ls2085qds: Add support ethernet
Add support of ethernet:
 - eth.c: mapping lane to slot for (0x2A, 0x07)
 - ls2085a.c: To enable/disable dpmac and get link type

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Prabhakar Kushwaha
9cc2c4713a driver/ldpaa: Add support of WRIOP static data structure
Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC.  Here Each WRIOP block supports
upto 64 DPMACs.

Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:58 -07:00
Prabhakar Kushwaha
c517771ae7 driver/ldpaa_eth: Add LDPAA Ethernet driver
LDPAA Ethernet driver is a freescale's new ethernet driver based on
Layerscape architecture.

Every ethernet driver controls on DPNI object. Where all DPNIs share
one common DPBP and DPIO object to support  Rx and Tx flows.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Cristian Sovaiala <cristian.sovaiala@freescale.com>
CC: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
CC: J. German Rivera <German.Rivera@freescale.com>
[York Sun: s/NetReceive/net_process_received_packet]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:17 -07:00