Commit graph

71864 commits

Author SHA1 Message Date
Lad Prabhakar
6180db6e56 arm: dts: r8a774c0: Resync R8A774C0 SoC DTSI with Linux 5.11
Resync the R8A774C0 SoC DTSI with Linux kernel 5.11 commit f40ddce88593
("Linux 5.11").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Biju Das
5be85de6a8 arm: rmobile: Add HopeRun HiHope RZ/G2H board support
The HiHope RZ/G2H board from HopeRun consists of main board
(HopeRun HiHope RZ/G2H main board) and sub board(HopeRun
HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits
below the HiHope RZ/G2H main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2H board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Biju Das
dca070c382 arm: rmobile: Add HopeRun HiHope RZ/G2N board support
The HiHope RZ/G2N board from HopeRun consists of main board
(HopeRun HiHope RZ/G2N main board) and sub board(HopeRun
HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits
below the HiHope RZ/G2N main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2N board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Biju Das
b650c83825 arm: rmobile: Add HopeRun HiHope RZ/G2M board support
The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Biju Das
40ac794524 arm: dts: rmobile: r8a774e1: Synchronize DTs with Linux 5.11
Synchronize r8a774e1 device trees with Linux 5.11,
commit f40ddce88593482919 ("Linux 5.11").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Biju Das
2141203f58 arm: dts: rmobile: r8a774b1: Synchronize DTs with Linux 5.11
Synchronize r8a774b1 device trees with Linux 5.11,
commit f40ddce88593482919 ("Linux 5.11")

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2021-03-16 20:09:29 +01:00
Tom Rini
22fc991daf Prepare v2021.04-rc4
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmBPhiUACgkQFHw5/5Y0
 tywChgv/RYpdSKrD5s4kCJnImfOwDznESj/CqAQK3Au5zviq7qXRrgxyTKv2e1wM
 W51vUBd0cE1YTACXqbr92wSSyqoTthLqd57KQgVele5uC2dvkqVTSvjPOUwtyIbQ
 BTPkoQnHPn30AILRdPjpEdBGfZhJDDtJFdQopn6h4GjEjPKVH8Wx1Dd+V6SD5f20
 WiksUjgdjMr1AmORY+LdwwJO8FZrGGPYgs8CDtiqxmCSwh3d7kUFFTT+G23BZdo7
 M+81+1uIUaW2Bolds7ZTPrrjr8bPwkWoTqNYhUB4bNPLp72gwnjM1rtU1X3hyiJM
 MdxSBimLHUOYPihfeSYCHSUrJaQFAAEFkuzWfZN1fgoswKEZQIVVVTzT/TomTyqf
 1DIXD+0HpXGKgVLW/Nkpl4D+UFjR865XI4kiuDxddjKI7bGbvDlbZ/k3PNelD7op
 umUswHnC3OTSw/g+A9VH/zf1rMFNLfu++vD7XJtdoWlcsl6x6/6Fh75tuC6K/X0K
 caPmehD3
 =ENym
 -----END PGP SIGNATURE-----

Merge tag 'v2021.04-rc4' into next

Prepare v2021.04-rc4
2021-03-15 12:15:38 -04:00
Tom Rini
4103e13534 Prepare v2021.04-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-03-15 12:06:41 -04:00
Tom Rini
6ad0769c8e configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-03-15 10:50:47 -04:00
Tom Rini
23986be8ca Merge tag 'ti-v2021.04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Fix boot for da850-evm and omap3_logic
- Optimize SPL size for am65x boards
2021-03-15 08:43:29 -04:00
Tom Rini
e8a10a02bd - Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
- stm32mp1_trusted_defconfig rely on SCMI support
 - Remove the nand MTD configuration for NOR boot in stm32mp1 board
 - STM32programmer update
 - Bsec: manage clock when present in device tree
 - stm32mp15: move bootdelay configuration in defconfig
 - Update for stm32 dsi and dw_mipi_dsi
 - STM32 MCU's cleanup
 - Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
 - Update stm32mp1 doc
 -----BEGIN PGP SIGNATURE-----
 
 iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmBLfA8cHHBhdHJpY2Uu
 Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/pkNnD/4hQrwBdaJMz9YXL4Tp
 0W7kpCcTkG+gINY06BONNnKzBHq62SkWMo/lw9iF0nlcNKSOHzrz6ttm+e54ngs0
 qe/dn0yjgImDfr5p5JRMTG1m7/XwQpucZ8wowSZAwt5f/DDh9eta9AyST0ev+iXI
 Eqgbk5HsF2OCOK6h74FJidZUdLMLw+uQkIwPhglx3ZaxxFfXHAdWtXtJ9Fky2adU
 BC0PltvJ6KYl1LTUGCQvrCST1sNe1PXPHrcsUpsQnqUSZ65tGKgeH2On9Exsw6cE
 eA5v0aiQSMmAH2pYXrJwxhSW9b03yt3NdBQd09Du2YUuFe7yZeoWIFy8mM9jRaov
 QDe88aJ9ZjxB+TvYQPToEL0EIyBGkN3HnX05BtKzKLf+E2+wP6gEf/6Sob7fBf6n
 3n2Eud0COfe06hNiocYOHm8n/8bZxdmuEgMA8LU0PZETbH33NlvJtrjyBxY4OHOV
 G+RG6J8idpVWWQ69g2TqfsVhXSjF893nvLOu0+KjuNrZWG4BVxGjylVUSvayk7bG
 TI++ZKlbdvJGweZ3uUPcNLH4VaX47P/nZS/6vX1uL7NtRNvv3jLHN5z4t6zKI9rh
 3iTJxxVv3zilWcY1WsoSdUvK56RTubnNwUlpjriabdRwMDjMN0isL9N06PvOELoi
 jU1IkKBLtMvPbb2XfLRIjvQjTQ==
 =nIJc
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20210312' of https://source.denx.de/u-boot/custodians/u-boot-stm

- Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
- stm32mp1_trusted_defconfig rely on SCMI support
- Remove the nand MTD configuration for NOR boot in stm32mp1 board
- STM32programmer update
- Bsec: manage clock when present in device tree
- stm32mp15: move bootdelay configuration in defconfig
- Update for stm32 dsi and dw_mipi_dsi
- STM32 MCU's cleanup
- Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
- Update stm32mp1 doc
2021-03-15 08:43:19 -04:00
Tom Rini
1876b390f3 Merge branch '2021-03-12-assorted-improvements' into next
- More log enhancements
- A few warning fixes in some cases
- Secure Channel Protocol 03 (SCP03) support for TEEs
2021-03-15 08:41:14 -04:00
Lokesh Vutla
f72edfddde configs: am65x_evm_r5: Enable checks for spl and stack sizes
Enable relevant configs that checks for the size of image and stack:

 BSS: 3KB
 Initial MALLOC: ~22KB
 Initial Stack: 8K
 SPL Image size can be: ~215KB

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-03-15 12:13:44 +05:30
Lokesh Vutla
003d10ba64 include: configs: am65x_evm: Optimize size of SPL BSS
Current BSS allocation of SPL is as below:
$ size spl/u-boot-spl
   text	   data	    bss	    dec	    hex	filename
 132369	   7852	   1496	 141717	  22995	spl/u-boot-spl

But 20KB is allocated currently for BSS. Reduce it to 3KB and save some
space for stack.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-03-15 12:13:44 +05:30
Adam Ford
a69c48959b ARM: da850-evm: Fix boot issues from missing SPL_PAD_TO
In a previous attempt to unify config options and remove items
from the whitelist file, SPL items were moved into a section
enabled with CONFIG_SPL_BUILD.  Unfortunately, SPL_PAD_TO
is referenced at the head Makefile and uses this define
to create padding of the output file.  When it was moved
to CONFIG_SPL_BUILD, it caused boot errors with devices
that are not booting from NOR.  Fix the boot issues by moving
SPL_PAD_TO out so it's always.

Fixes: 7bb33e4684 ("ARM: da850-evm: Unify config options with Kconfig")
Signed-off-by: Adam Ford <aford173@gmail.com>
2021-03-15 11:11:20 +05:30
Adam Ford
136284a3cf configs: omap3_logic: Enable CONFIG_SPL_ALLOC_BD
With bd_info dropped from the data section, the Logic PD OMAP3 boards
and AM3517 fail to boot. Enabling CONFIG_SPL_ALLOC_BD restores
them.

Fixes: 38d6b7ebda ("spl: Drop bd_info in the data section")
Signed-off-by: Adam Ford <aford173@gmail.com>
2021-03-15 11:10:46 +05:30
Igor Opaniuk
7f047b4f5b test: py: add initial coverage for scp03 cmd
Add initial test coverage for SCP03 command.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-14 11:50:16 -04:00
Igor Opaniuk
7c591a841c sandbox: imply SCP03 and CMD_SCP03
Enable by default SCP_03/CMD_SCP03 for sandbox target.

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-14 11:50:16 -04:00
Jorge Ramirez-Ortiz
ffd8483b3c doc: describe the scp03 command
The Secure Channel Protocol 03 command sends control requests
(enable/provision) to the TEE implementing the protocol between the
processor and the secure element.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-14 11:50:16 -04:00
Jorge Ramirez-Ortiz
5a8783c80c drivers: tee: sandbox: SCP03 control emulator
Adds support for a working SCP03 emulation. Input parameters are
validated however the commands (enable, provision) executed by the TEE
are assumed to always succeed.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-14 11:50:13 -04:00
Jorge Ramirez-Ortiz
26839e5dde cmd: SCP03: enable and provision command
Enable and provision the SCP03 keys on a TEE controlled secured elemt
from the U-Boot shell.

Executing this command will generate and program new SCP03 encryption
keys on the secure element NVM.

Depending on the TEE implementation, the keys would then be stored in
some persistent storage or better derived from some platform secret
(so they can't be lost).

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-03-13 13:14:52 -05:00
Jorge Ramirez-Ortiz
166363f2ed common: SCP03 control (enable and provision of keys)
This Trusted Application allows enabling SCP03 as well as provisioning
the keys on TEE controlled secure element (ie, NXP SE050).

All the information flowing on buses (ie I2C) between the processor
and the secure element must be encrypted. Secure elements are
pre-provisioned with a set of keys known to the user so that the
secure channel protocol (encryption) can be enforced on the first
boot. This situation is however unsafe since the keys are publically
available.

For example, in the case of the NXP SE050, these keys would be
available in the OP-TEE source tree [2] and of course in the
documentation corresponding to the part.

To address that, users are required to rotate/provision those keys
(ie, generate new keys and write them in the secure element's
persistent memory).

For information on SCP03, check the Global Platform HomePage and
google for that term [1]
[1] globalplatform.org
[2] https://github.com/OP-TEE/optee_os/
    check:
    core/drivers/crypto/se050/adaptors/utils/scp_config.c

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-13 13:14:52 -05:00
Simon Glass
2a8dc4c488 doc: sandbox: Update instructions on quitting
The 'reset' command now resets sandbox but does not quit it. Fix the
instructions.

Fixes: 329dccc067 ("sandbox: implement reset")
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-13 13:14:52 -05:00
Simon Glass
634f5ad3ae test: acpi: Fix warnings on 32-bit build
Some format strings use the wrong type. Fix them.

Example warnings:

In file included from test/dm/acpi.c:22:
test/dm/acpi.c: In function ‘dm_test_acpi_cmd_list’:
test/dm/acpi.c:362:21: warning: format ‘%lx’ expects argument of type
  ‘long unsigned int’, but argument 4 has type ‘unsigned int’ [-Wformat=]
  ut_assert_nextline("RSDP %08lx %06lx (v02 U-BOOT)", addr,
                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
       sizeof(struct acpi_rsdp));
       ~~~~~~~~~~~~~~~~~~~~~~~~
include/test/ut.h:282:33: note: in definition of macro ‘ut_assert_nextline’
  if (ut_check_console_line(uts, fmt, ##args)) {   \
                                 ^~~

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-13 13:14:52 -05:00
Simon Glass
e7c920a228 tpm: Correct warning on 32-bit build
Fix the warning:

drivers/tpm/tpm2_tis_sandbox.c: In function ‘sandbox_tpm2_xfer’:
drivers/tpm/tpm2_tis_sandbox.c:288:48: warning: format ‘%ld’ expects
	argument of type ‘long int’, but argument 2 has type ‘size_t’
	{aka ‘unsigned int’} [-Wformat=]
   printf("TPM2: Unmatching length, received: %ld, expected: %d\n",
                                              ~~^
                                              %d
          send_size, length);
          ~~~~~~~~~

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-03-13 13:14:52 -05:00
Simon Glass
9586a48173 tpm: Don't select LOG
We don't need to enable logging to run this command since the output will
still appear. Drop the 'select'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 17:41:35 -05:00
Simon Glass
7bd06587de log: Add return-checking macros for 0 being success
The existing log_ret() and log_msg_ret() macros consider an error to be
less than zero. But some function may return a positive number to indicate
a different kind of failure. Add macros to check for that also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 17:41:35 -05:00
Simon Glass
9ad7a6c25c log: Handle line continuation
When multiple log() calls are used which don't end in newline, the
log prefix is prepended multiple times in the same line. This makes the
output look strange.

Fix this by detecting when the previous log record did not end in newline.
In that case, setting a flag.

Drop the unused BUFFSIZE in the test while we are here.

As an example implementation, update log_console to check the flag and
produce the expected output.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 17:41:35 -05:00
Simon Glass
79d5983b61 log: Set up a flag byte for log records
At present only a single flag (force_debug) is used in log records. Before
adding more, convert this into a bitfield, so more can be added without
using more space.

To avoid expanding the log_record struct itself (which some drivers may
wish to store in memory) reduce the line-number field to 16 bits. This
provides for up to 64K lines which should be enough for anyone.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 17:41:35 -05:00
Tom Rini
c57ec2c2ba Merge branch '2021-03-12-test-improvements' into next
- Assorted improvements to the pytest framework
2021-03-12 15:57:20 -05:00
Simon Glass
fc32833145 doc: Explain briefly how to write new tests
Add a second on writing tests, covering when to use Python and C, where
to put the tests, etc. Add a link to the existing Python test
documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:31 -05:00
Simon Glass
e1b12e3945 test: sandbox: Move sandbox test docs into doc/develop
At present some of the documentation about running sandbox tests is in the
sandbox docs. It makes more sense to put it in with the other testing
docs, with a link there from sandbox. Update the documentation
accordingly.

Also add a paragraph explaining why sandbox exists and the test philosophy
that it uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:31 -05:00
Simon Glass
2e059e4a6e spl: test: Add a test for spl_load_simple_fit()
As an example of an SPL test, add a new test for loading a FIT within
SPL. This runs on sandbox_spl. For this to work, the text base is adjusted
so that there is plenty of space available.

While we are here, document struct spl_load_info properly, since this is
currently ambiguous.

This test only verifies the logic path. It does not actually check that
the image is loaded correctly. It is not possible for sandbox's SPL to
actually run u-boot.img since it currently includes u-boot.bin rather than
u-boot. Further work could expand the test in that direction.

The need for this was noted at:

   http://patchwork.ozlabs.org/project/uboot/patch/20201216000944.2832585-3-mr.nuke.me@gmail.com/

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:31 -05:00
Simon Glass
891d9e84a7 spl: Convert spl_fit to work with sandbox
At present this casts addresses to pointers so cannot work with sandbox.
Update the code to use map_sysmem() instead.

As part of this change, the existing load_ptr is renamed to src_ptr since
it is not a pointer to load_addr. It is confusing to use a similar name
for something that is not actually related. For the alignment code,
ALIGN() is used instead of open-coded alignment. Add a comment to the line
that casts away a const.

Use a (new) load_ptr variable to access memory at address load_addr.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:31 -05:00
Simon Glass
01ad9f75c5 sandbox: Update os_find_u_boot() to find the .img file
At present this function can only locate the u-boot ELF file. For SPL it
is handy to be able to locate u-boot.img since this is what would normally
be loaded by SPL.

Add another argument to allow this to be selected.

While we are here, update the function to load SPL when running in TPL,
since that is the next stage.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:31 -05:00
Simon Glass
8482356f48 test: Allow SPL to run any available test
At present SPL only runs driver model tests. Update it to run all
available tests, i.e. in any test suite.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:31 -05:00
Simon Glass
2a2814d5f2 test: Rename all linker lists to have a ut_ prefix
At present each test suite has its own portion of the linker_list section
of the image, but other lists are interspersed. This makes it hard to
enumerate all the available tests without knowing the suites that each one
is in.

Place all tests together in a single contiguous list by giving them
common prefix not used elsewhere in U-Boot. This makes it possible to find
the start and end of all tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
a7a98755b8 test: Add a macros for finding tests in linker_lists
At present we use the linker list directly. This is not very friendly, so
add a helpful macro instead. This will also allow us to change the naming
later without updating this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
5c1cf4d2da test: log: Rename log main test file to log_ut.c
The current name is the same as the main test runner file. Rename it to
avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-03-12 09:57:30 -05:00
Simon Glass
664277f106 test: Move restoring of driver model state to ut_run_list()
Add this functionality to ut_run_list() so it can be removed from
dm_test_run().

At this point all tests are run through ut_run_list().

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
1fc9c12210 test: Move the devicetree check into ut_run_list()
Add a check to ut_run_list() as to whether a list has driver model tests.
Move the logic for the test devicetree into that function, in an effort
to eventually remove all logic from dm_test_run().

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
45d191af02 test: Use return values in dm_test_run()
Update this function to use the return value of ut_run_list() to check for
success/failure, so that they are in sync. Also return a command success
code so that the caller gets what it expects.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
f97f85e661 test: Run driver-model tests using ut_run_list()
Use this function instead of implementing it separately for driver model.

Make ut_run_tests() private since it is only used in test-main.c

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
fe806861a9 test: Use a local variable for test state
At present we use a global test state for all driver-model tests. Make use
of a local struct like we do with the other tests.

To make this work, add functions to get and set this state. When a test
starts, the state is set (so it can be used in the test). When a test
finishes, the state is unset, so it cannot be used by mistake.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
d2281bb09b test: Add ut_run_test_live_flat() to run tests twice
Driver model tests are generally run twice, once with livetree enable and
again with it disabled. Add a function to handle this and call it from the
driver model test runner.

Make ut_run_test() private since it is not used outside test-main.c now.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
c169d542bb test: Drop dm_do_test()
In an effort to make use of a common test runner, use ut_run_test()
directly to run driver model tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
ca44ca0556 test: Use ut_run_test() to run driver model tests
Instead of having a separate function for running driver model tests, use
the common one. Make the pre/post-run functions private since we don't
need these outside of test-main.c

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
99a88fe1bd test: Move test running into a separate function
Add a function to handle the preparation for running a test and the
post-test clean-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
e77615d3a7 test: Move dm_test_destroy() into test-main.c
Move this function into the common test runner and rename it to
dm_test_post_run() so that its purpose is clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00
Simon Glass
c79705ea93 test: Move dm_test_init() into test-main.c
Move this function into test-main so that all the init is in one place.
Rename it so that its purpose is clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-12 09:57:30 -05:00