* 'master' of git://git.denx.de/u-boot-arm:
ARM: MX5: Fix broken leftover TO-2 errata workaround
MX31: Cleanup clock function
scb9328: Add ARM relocation support
am3517evm: change console device from ttyS2 to ttyO2
Remove volatile qualifier in get_ram_size() calls
TI: TNETV107X Fix Build Error
ARM: add missing CONFIG_SKIP_LOWLEVEL_INIT for armv7
arm: add CONFIG_MACH_TYPE setting and documentation
arm: add __ilog2 function
Timer: Fix misuse of ARM *timer_masked() functions outside arch/arm
EfikaMX: Enable EXT2 booting
EfikaMX: Add missing CONFIG_SYS_TEXT_BASE
EfikaMX: Use correct imximage.cfg
MX27: Update to autogenerated asm-offsets.h
MX5: Update to autogenerated asm-offsets.h
imx: Add support for zmx25 board
imx: Make imx25 compatible to mxc_gpio driver and fix in tx25
imx: Add auto generation of asm-offsets.h for imx25
imx: Add support for USB EHCI on imx25
imx: Use correct imx25 reset.c
imx: Add get_tbclk() function for imx25
ARM: Update maintainer of board scb9328
mx27: Make the UART port number explicit
build: Add targets for auto gen of asm-offsets.h and use it in imx35
mx31pdk: cosmetic: Fix line over 80 characters
P2041RDB Specification:
-----------------------
Memory subsystem:
* 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
* 128 Mbyte NOR flash single-chip memory
* 256 Kbit M24256 I2C EEPROM
* 16 Mbyte SPI memory
* SD connector to interface with the SD memory card
Ethernet:
* dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
* dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
PCIe:
* Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
* Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2
SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
I2C:
* I2C1: Real time clock, Temperature sensor, Memory module
* I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Checkpatch.pl complains about the volatile qualifier in calls to
get_ram_size(). Remove this qualifier in the prototype and in the
calls where it is useless, and leave it only in the function body
where it is needed.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Resolve P1020 second USB controller multiplexing with eLBC
- mandatory to mention USB2 in hwconfig string to select it
over eLBC, otherwise USB2 node is removed
- works only for SPI and SD boot
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P1023RDS board is the reference board for the P1023 SoC.
Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe,
UART, I2C, etc.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If DDR initialziation uses a speed table and the speed is not matched,
print a warning message instead of silently ignoring.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Allow overriding RCW for all RDIMM, not only quad-rank ones.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add ifdef protection for qp_info and liodn associated with Q/BMan. Also
rearrange setting of _tbl_sz variables to utilize existing ifdef
protection for things like FMAN.
Also add protection around setup_portals() call in corenet_ds board
code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add ifdef protection in LAW & TLB code to handle the case in which
CONFIG_SYS_BMAN_MEM_PHYS or CONFIG_SYS_QMAN_MEM_PHYS arent defined for a
build.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove an empty board_early_init_f() from the MPC8323ERD and MPC360ERDK boards.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The clock-frequency property in an audio codec's device tree node is set to
the input clock frequency for that codec. On the Freescale P1022DS board,
the input clock is enabled only if the hwconfig 'audclk' option is set.
Therefore, the property should only be set in the device tree if the clock
is actually enabled.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This fixes the MX31ADS build by using the new relocation scheme.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Felix Radensky <felix@embedded-sol.com>
The boot cause code has been factor out to soc common
code,we need drop the part from the board support code
This patch also remove the redundant cpu version print
Signed-off-by: Jason Liu <jason.hui@linaro.org>
This patch add initial support for freescale MX53LOCO board.
Network(FEC),SD/MMC,UART have been supported by this patch
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Currently, some linker scripts are found by common code in config.mk.
Some are found using CONFIG_SYS_LDSCRIPT, but the code for that is
sometimes in arch config.mk and sometimes in board config.mk. Some
are found using an arch-specific rule for looking in CPUDIR, etc.
Further, the powerpc config.mk rule relied on CONFIG_NAND_SPL
when it really wanted CONFIG_NAND_U_BOOT -- which covered up the fact
that not all NAND_U_BOOT builds actually wanted CPUDIR/u-boot-nand.lds.
Replace all of this -- except for a handful of boards that are actually
selecting a linker script in a unique way -- with centralized ldscript
finding.
If board code specifies LDSCRIPT, that will be used.
Otherwise, if CONFIG_SYS_LDSCRIPT is specified, that will be used.
If neither of these are specified, then the central config.mk will
check for the existence of the following, in order:
$(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT)
$(TOPDIR)/$(CPUDIR)/u-boot-nand.lds (only if CONFIG_NAND_U_BOOT)
$(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
$(TOPDIR)/$(CPUDIR)/u-boot.lds
Some boards (sc3, cm5200, munices) provided their own u-boot.lds that
were dead code, because they were overridden by a CPUDIR u-boot.lds under
the old powerpc rules. These boards' own u-boot.lds have bitrotted and
no longer work -- these lds files have been removed.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Tested-by: Graeme Russ <graeme.russ@gmail.com>
Add the 'pixis_reset dump' command, which displays the contents of the PIXIS
registers. This command is only available if DEBUG is defined.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove an empty board_early_init_f() from the MPC8641HPCN board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use the 'video-mode' environment variable (for Freescale chips that have a
DIU display controller) to designate the full video configuration. Previously,
the DIU driver used the 'monitor' variable, and it was used only to determine
the output video port.
The old definition of the "monitor" environment variable only determines
which video port to use for output. This variable was set to a number (0,
1, or sometimes 2) to specify a DVI, LVDS, or Dual-LVDS port. The
resolution was hard-coded into board-specific code. The Linux command-line
arguments needed to be hard-coded to the proper video definition string.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
The P3041DS & P5020DS boards are almost identical (except for the
processor in them). Additionally they are based on the P4080DS board
design so we use the some board code for all 3 boards.
Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have
meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock
configuration.
Additionally, the P3041DS/P5020DS support NAND.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
As exception among the i.MX processors, the i.MX31 has headers
without general names (mx31-regs.h, mx31.h instead of imx-regs.h and
clock.h). This requires several nasty #ifdef in the drivers to
include the correct header. The patch cleans up the driver and
renames the header files as for the other i.MX processors.
Signed-off-by: Stefano Babic <sbabic@denx.de>
The config.mk file in board directory is now obsolete and
should be removed. Add option for the IMX image into
boards.cfg
Signed-off-by: Jason Liu <r64343@freescale.com>
The config.mk file in board directory is now obsolete and
should be removed. Add option for the IMX image into
boards.cfg
Signed-off-by: Stefano Babic <sbabic@denx.de>
The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum.
This meant that drivers which used fsl_phy_enet_if to deal with
PHY interfaces would have to convert between the two (or we would have
to have them mirror each other, and deal with the ensuing maintenance
headache). Instead, we switch all clients of fsl_phy_enet_if over to
phy_interface_t, which should become the standard, anyway.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Detlev Zundel <dzu@denx.de>
This converts tsec to use the new PHY Lib. All of the old PHY support
is ripped out. The old MDIO driver is split off, and placed in
fsl_mdio.c. The initialization is modified to initialize the MDIO
driver as well. The powerpc config file is modified to configure PHYLIB
if TSEC_ENET is configured.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as
1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from
CPC after PBL completes RCW and PBI phases.
Signed-off-by: Chunhe Lan <b25806@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For soc which have pin multiplex relation, some of them can't enable
simultaneously. This patch add environment var 'hwconfig' content
defination for them. you can enable some one function by setting
environment var 'hwconfig' content and reset board. Detail setting
please refer doc/README.p1022ds
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We implement our own mmc_get_env_addr since the environment variables are
written to just after the u-boot image on SDCard, so we must read the MBR
to get the start address and code length of the u-boot image, then
calculate the address of the env.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for 36-bit address map for NOR, SD, and SPI boot cfgs.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Changed the following DDR timing parameters for 800Mt/s:
tRRT BL/2+1 to BL/2
tWWT BL/2+1 to BL/2
tWRT BL/2+1 to BL/2
tRWT BL/2+1 to BL/2
REFINT 6500ns to 7800ns
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
RevB boards never really made it outside of Freescale and have been
replaced with RevC & RevD which had various board bug fixes.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
PCA9557 is parallel I/O expansion device on I2C bus which stores various
board switch settings like NOR Flash-Bank selection, SD Data width.
On board:
switch SW5[6] is to select width for eSDHC
ON - 4-bit [Enable eSPI]
OFF - 8-bit [Disable eSPI]
switch SW4[8] is to select NOR Flash Bank for Booting
OFF - Primary Bank
ON - Secondary Bank
Read board switch settings on p1_p2_rdb and configure corresponding
eSDHC width.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash
boot loaders because:
- P1_P2_RDB boards have soldered DDR so no need for SPD
- Also P102x has 256K L2 cache size so becomes a limiting factor for
size of image that could be loaded in SRAM mode and would require three
stage boot loader (TPL).
Changes done:
1. CONFIG_SYS_TEXT_BASE to 0x11000000
2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The NXID EEPROM format comes in two versions, v0 and v1. The only
difference is in the number of MAC addresses that can be stored. NXID v0
supports eight addresses, and NXID v1 supports 23.
Rather than allow a board to choose which version to support, NXID v0 is
now considered deprecated. The EEPROM code is updated to support only
NXID v1, but it can still read EEPROMs formatted with v0. In these cases,
the EEPROM data is loaded and the CRC is verified, but the data is stored
into a v1 data structure. If the EEPROM data is written back, it is
written in v1 format. This allows existing v0-formatted EEPROMs to
continue providing MAC addresses, but any changes to the data will force
an upgrade to the v1 format, while retaining all data.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.
We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move the include of mpc85xx/u-boot-nand.lds to utilize
CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems. We can just move this into arch_lmb_reserve for 85xx & 86xx
systems rather than duplicating in each board port.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9
respectively).
We enable EXT2, FAT, and parition support for both MMC & USB configs.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
