Commit graph

2105 commits

Author SHA1 Message Date
Linus Walleij
23b5877c64 armv8/vexpress64: make multientry conditional
While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.

The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.

Make the single entry default and add a special
ARMV8_MULTIENTRY KConfig option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.

This makes the Juno platform start U-Boot properly.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09 11:13:29 -04:00
Tom Rini
dd09f7e73c ARM: PSCI: Rework the DT handler slightly
The way the PSCI DT update happens currently means we pull in
<asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in
<asm/io.h> for some non-PSCI related things that header needs to deal
with.

To fix this, we rework the hook slightly.  A good portion of
arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI
is needed on ARMv8 we can re-use this by and large.  So rename the
current hook to psci_update_dt(), move the prototype to <asm/psci.h> and
add an #ifdef that will make re-use later easier.

Reported-by: York Sun <yorksun@freescale.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: York Sun <yorksun@freescale.com>
2015-03-09 11:13:29 -04:00
Tom Rini
1c6f6a6ef9 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-03-05 20:50:30 -05:00
gaurav rana
e04916a721 SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.
esbc_validate command uses various IP Blocks: Security Monitor, CAAM block
and SFP registers. Hence the respective CONFIG's are enabled.

Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-05 12:04:59 -08:00
Tom Rini
02ebe6f702 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-03-05 07:22:18 -05:00
Stefano Babic
32df39c741 mx5: fix get_reset_cause
commit d9f43c8f5c sets
get_reset_cause() as static, but this conflicts with mx5
where its prototype is in sys_proto.h.

Drop it from sys_proto.h and drop print_cpuinfo from mx53_loco,
factorizing the call for this board.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <jason.hui@linaro.org>
2015-03-05 10:29:27 +01:00
Simon Glass
fc8fdc76e7 arm: spl: Avoid setting up a duplicate global data structure
This is already set up in crt0.S. We don't need a new structure and don't
really want one in the 'data' section of the image, since it will be empty
and crt0.S's changes will be ignored.

As an interim measure, remove it only if CONFIG_DM is not defined. This
allows us to press ahead with driver model in SPL and allow the stragglers
to catch up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-04 14:55:04 -05:00
Tom Rini
7547f78ce2 Merge branch 'xnext/zynqmp' of git://www.denx.de/git/u-boot-microblaze 2015-03-02 13:22:12 -05:00
Michal Simek
84c7204bd1 arm64: Add Xilinx ZynqMP support
Add basic Xilinx ZynqMP arm64 support.
Serial and SD is supported.
It supports emulation platfrom ep108 and QEMU.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-02 18:41:54 +01:00
Tom Rini
301c128379 armv7.h: Add <asm/io.h>
With a389531 we now call readl() from this file so add <asm/io.h> so
that we have a prototype for the function.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-03-02 08:24:45 -05:00
Raul Cardenas
0200020bc2 imx6: Added DEK blob generator command
Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a AES-256 key is randomly generated to encrypt the DEK.
This key is encrypted with the OTP Secret key
from SoC. The resulting blob consists of the encrypted
AES-256 key, the encrypted DEK, and a 16-bit MAC.

During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process,  is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.

Commands added
--------------
  dek_blob - encapsulating DEK as a cryptgraphic blob

Commands Syntax
---------------
  dek_blob src dst len

    Encapsulate and create blob of a len-bits DEK at
    address src and store the result at address dst.

Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>

Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com>

Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
2015-03-02 09:57:06 +01:00
Stefano Babic
b9cb64825b Merge branch 'master' of git://git.denx.de/u-boot 2015-03-02 09:42:53 +01:00
Tom Rini
6fa361903c Merge branch 'master' of git://git.denx.de/u-boot-samsung 2015-03-01 22:05:54 -05:00
Tom Rini
1da7ce4155 Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2015-03-01 21:07:53 -05:00
Tom Rini
fc83410095 Merge branch 'rmobile' of git://git.denx.de/u-boot-sh 2015-03-01 21:06:47 -05:00
Masahiro Yamada
9eb7acef97 ARM: UniPhier: move SoC headers to mach-uniphier/include/mach
Move arch/arm/include/asm/arch-uniphier/*
  -> arch/arm/mach-uniphier/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:12 +09:00
Doug Anderson
306f527eff Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800
It was found that the L2 cache timings that we had before could cause
freezes and hangs.  We should make things more robust with better
timings.  Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).

This also provides a big cleanup of the L2 cache init code avoiding
some duplication.  The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
  time) and left resident in iRAM for the kernel to use when bringing
  up additional CPUs.  It used configure_l2_ctlr() and
  configure_l2_actlr() when it detected it was on an A15.  This was
  needed (despite the L2 cache registers being shared among all A15s)
  because we might have been the first man in after the whole A15
  cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
  time.  Strangely this called configure_l2_ctlr() but not
  configure_l2_actlr() which was almost certainly wrong.  Given that
  we'll call both (see next bullet) later in the boot process it
  didn't matter for normal boot, but I guess this is how L2 cache
  settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
  This should happen at boot time (normally in the SPL except for USB
  boot where it happens in main U-Boot).

Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time.  For resume time we'd get it
anyway when the 2nd A15 core came up.

Let's make this a whole lot simpler.  Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.

Intended net effects of this change (other than cleanup):
* Timings go from before:
    data: 0 cycle setup, 3 cycles (0x2) latency
    tag:  0 cycle setup, 3 cycles (0x2) latency
  after:
    data: 1 cycle setup, 4 cycles (0x3) latency
    tag:  1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.

One note is that we're still relying on luck to keep low_power_start()
working.  The compiler is being nice and not storing anything on the
stack.

Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL.  The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
  (after it has turned the L2 cache off).  This is why the functions
  are in a header file instead of lowlevel_init.c.

* Have the kernel save the L2 cache settings of the boot CPU and apply
  them to all other CPUs.  We get a little lucky here because the old
  code was using "|=" to modify the registers and all of the bits that
  it's setting are also present in the new settings (!).  That means
  that when the 2nd CPU in the A15 cluster comes up it doesn't
  actually mess up the settings of the 1st CPU in the A15 cluster.  An
  alternative option is to have the kernel write its own
  low_power_start() code.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-28 18:03:46 +09:00
Akshay Saraswat
cecf2db23b Exynos542x: Fix secondary core booting for thumb
When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of "bx" ARM instruction.
"bx" instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-28 18:03:46 +09:00
Akshay Saraswat
a389531439 Exynos542x: Add workaround for ARM errata 799270
This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-28 18:03:46 +09:00
Akshay Saraswat
0c08baf053 Exynos542x: Add workaround for ARM errata 798870
This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-28 18:03:46 +09:00
Akshay Saraswat
ac0d98cd55 Exynos542x: CPU: Power down all secondary cores
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.

Secondary core power down happens in following steps:

Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
	addresses 0x02020028 & 0x02020004.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
	jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and jumps
	to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function secondary_cores_configure,
	it puts pointer to function power_down_core into 0x02020004
	and provides DSB and SEV for all cores so that they may come out
	of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
	secondary cores shut-down.

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-28 18:03:46 +09:00
Tom Rini
1606b34aa5 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-02-25 18:14:18 -05:00
Nobuhiro Iwamatsu
25f9613fcf arm: rmobile: alt: Add support SDHI
Alt board has two SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2015-02-25 13:13:38 +09:00
Masahiro Yamada
50b82c4b70 ARM: remove tnetv107x board support
This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chan-Taek Park <c-park@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-02-24 17:07:24 -05:00
Masahiro Yamada
29fc6f2492 ARM: remove a320evb board support
This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Po-Yu Chuang <ratbert@faraday-tech.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-02-24 17:07:17 -05:00
Masahiro Yamada
a2f39e830e ARM: remove cm4008 and cm41xx board support
These are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Greg Ungerer <greg.ungerer@opengear.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-02-24 17:07:11 -05:00
Masahiro Yamada
346cfba4f0 ARM: remove dkb board support
This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Lei Wen <leiwen@marvell.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-02-24 17:07:03 -05:00
Masahiro Yamada
41fbbbbc71 ARM: remove jadecpu board support
This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Matthias Weisser <weisserm@arcor.de>
Acked-by: Marek Vasut <marex@denx.de>
2015-02-24 17:06:51 -05:00
Alison Wang
8133574ea4 arm: ls1021x: Add support for initializing CAAM's stream id
There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id
for using the same SMMU3 on LS1021A.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:11:05 -08:00
Minghuan Lian
ec245fd74d arm/ls102xa: use a array to define pexmscportsr
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:37 -08:00
Minghuan Lian
636ef95605 arm/ls102xa: create TLB to map PCIe region
LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins
0x48_00000000. In order to access PCIe device, we must create
TLB to map the 40bit physical address to 32bit virtual address.
This patch will enable MMU after DDR is available and creates MMU
table in DRAM to map all 4G space; then, re-use the reserved space
to map PCIe region. The following the mapping layout.

VA mapping:
    -------  <---- 0GB
   |       |
   |       |
   |-------| <---- 0x24000000
   |///////|  ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
   |-------| <---- 0x300000000
   |       |
   |-------| <---- 0x34000000
   |///////|  ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
   |-------| <---- 0x40000000
   |       |
   |-------| <---- 0x80000000 DDR0 space start
   |\\\\\\\|
   |\\\\\\\|  ===> 2GB VA map for 2GB DDR0 Memory space
   |\\\\\\\|
   -------  <---- 4GB DDR0 space end

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:31 -08:00
Alison Wang
60d517369c arm: ls102xa: Define default values for some CCSR macros
This patch is to define default values for some CCSR macros
to make header files cleaner.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:26 -08:00
York Sun
1478fdef52 armv8/fsl-lsch3: Enable erratum workround for A008514
Erratum A008514 appleis to ls2085a.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:12 -08:00
York Sun
a5ebdf06a0 armv8/fsl-lsch3: Enable workaround for A008336
Erratum A008336 applied to LS2085A.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:08 -08:00
York Sun
b87e6f88e9 armv8/fsl-lsch3: Add support for second DDR clock
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:14 -08:00
York Sun
9955b4ab01 driver/ddr/fsl: Add workaround for A008336
Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:06 -08:00
York Sun
dcd468b8f4 armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack
Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using
assembly function to guarantee stack is not used before flushing is
completed. Timeout is needed for simualtor on which CCN-504 is not
implemented. Return value can be checked for timeout situation.

Change bootm.c to disable dcache instead of simply flushing, required
by flushing L3.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:08:46 -08:00
York Sun
6c747f4ad4 armv8/fsl-lsch3: Change normal memory shareability
According to hardware implementation, a single outer shareable global
coherence group is defined. Inner shareable has not bee enabled.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:08:22 -08:00
Bhupesh Sharma
9c66ce662c fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accesses
This patch ensures that the TZPC (BP147) and TZASC-400 programming
happens for LS2085A SoC only when the desired config flags are
enabled and ensures that the TZPC programming is done to allow Non-secure
(NS) + secure (S) transactions only for DCGF registers.

The TZASC component is not present on LS2085A-Rev1, so the TZASC-400
config flag is turned OFF for now.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:08:06 -08:00
Otavio Salvador
8359318b5e imx: mx6sl: Extend USDHC SD2 pins to support 8-wire use
This adds the DATA[4-7] and RST pin definitions.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2015-02-23 09:11:43 +01:00
Peng Fan
9c3de876a1 imx:mx6sl add I2c pad settings
A few pad settings are I2C1

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-02-23 09:11:38 +01:00
Tom Rini
ded4bc3a8b Merge git://git.denx.de/u-boot-sunxi 2015-02-21 22:01:09 -05:00
Hans de Goede
f388a26d11 sunxi: Fix sun5i mbus speed when booting old kernels
Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
halving the mbus frequency, so set it to 300 MHz ourselves and base the
mbus divider on that.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-02-21 16:53:37 +01:00
Stephen Warren
4641429695 rpi: add support for Raspberry Pi 2 model B
USB doesn't seem to work yet; the controller detects the on-board Hub/
Ethernet device but can't read the descriptors from it. I haven't
investigated yet.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2015-02-21 08:28:16 -05:00
Stephen Warren
db75356f14 bcm2836 SoC support (used in Raspberry Pi 2 model B)
The bcm2835 and bcm2836 are essentially identical, except:
- The CPU is an ARM1176 v.s. a quad-core Cortex-A7.
- The physical address of many IO controllers has moved.

Rather than introducing a whole new bcm2836 value for $(SOC) or $(ARCH),
update the existing bcm2835 code to handle the minor differences, and
plumb it into the ARMv7 CPU architecture.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2015-02-21 08:27:48 -05:00
Stephen Warren
a033171b2e bcm2835/rpi: add SPDX license tags for some files
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2015-02-21 08:27:08 -05:00
Masahiro Yamada
dc7de222aa ARM: keystone: move SoC headers to mach-keystone/include/mach
Move arch/arm/include/asm/arch-keystone/*
  -> arch/arm/mach-keystone/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
2015-02-21 08:23:52 -05:00
Masahiro Yamada
fd697ecf5d ARM: orion5x: move SoC headers to mach-orion5x/include/mach
Move arch/arm/include/asm/arch-orion5x/*
  -> arch/arm/mach-orion5x/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-02-21 08:23:52 -05:00
Masahiro Yamada
5d0e6b28f3 ARM: nomadik: move SoC headers to mach-nomadik/include/mach
Move arch/arm/include/asm/arch-nomadik/*
  -> arch/arm/mach-nomadik/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
Cc: Alessandro Rubini <rubini@unipv.it>
2015-02-21 08:23:52 -05:00
Masahiro Yamada
ea3857230c ARM: kirkwood: move SoC headers to mach-kirkwood/include/mach
Move arch/arm/include/asm/arch-kirkwood/*
  -> arch/arm/mach-kirkwood/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-02-21 08:23:52 -05:00