More than one pumpkin board has been made with different MediaTek SoCs.
Rename the pumpkin board to follow the naming convention of all
other MediaTek boards and also to not be confusing when other pumpkin
boards will be added in follow-up commits.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
The EK874 development kit from Silicon Linux is made of CAT874 (the main
board) and CAT875 (the sub board that goes on top of CAT874).
This patch adds the required board support to boot Si-Linux EK874 board
based on R8A774C0 SoC.
DTS files apart from r8a774c0-ek874-u-boot.dts and r8a774c0-u-boot.dtsi
have been imported from Linux kernel 5.11 commit f40ddce88593
("Linux 5.11").
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.
This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
- stm32mp1_trusted_defconfig rely on SCMI support
- Remove the nand MTD configuration for NOR boot in stm32mp1 board
- STM32programmer update
- Bsec: manage clock when present in device tree
- stm32mp15: move bootdelay configuration in defconfig
- Update for stm32 dsi and dw_mipi_dsi
- STM32 MCU's cleanup
- Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
- Update stm32mp1 doc
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Merge tag 'u-boot-stm32-20210312' of https://source.denx.de/u-boot/custodians/u-boot-stm
- Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver
- stm32mp1_trusted_defconfig rely on SCMI support
- Remove the nand MTD configuration for NOR boot in stm32mp1 board
- STM32programmer update
- Bsec: manage clock when present in device tree
- stm32mp15: move bootdelay configuration in defconfig
- Update for stm32 dsi and dw_mipi_dsi
- STM32 MCU's cleanup
- Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags
- Update stm32mp1 doc
Current BSS allocation of SPL is as below:
$ size spl/u-boot-spl
text data bss dec hex filename
132369 7852 1496 141717 22995 spl/u-boot-spl
But 20KB is allocated currently for BSS. Reduce it to 3KB and save some
space for stack.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
In a previous attempt to unify config options and remove items
from the whitelist file, SPL items were moved into a section
enabled with CONFIG_SPL_BUILD. Unfortunately, SPL_PAD_TO
is referenced at the head Makefile and uses this define
to create padding of the output file. When it was moved
to CONFIG_SPL_BUILD, it caused boot errors with devices
that are not booting from NOR. Fix the boot issues by moving
SPL_PAD_TO out so it's always.
Fixes: 7bb33e4684 ("ARM: da850-evm: Unify config options with Kconfig")
Signed-off-by: Adam Ford <aford173@gmail.com>
This Trusted Application allows enabling SCP03 as well as provisioning
the keys on TEE controlled secure element (ie, NXP SE050).
All the information flowing on buses (ie I2C) between the processor
and the secure element must be encrypted. Secure elements are
pre-provisioned with a set of keys known to the user so that the
secure channel protocol (encryption) can be enforced on the first
boot. This situation is however unsafe since the keys are publically
available.
For example, in the case of the NXP SE050, these keys would be
available in the OP-TEE source tree [2] and of course in the
documentation corresponding to the part.
To address that, users are required to rotate/provision those keys
(ie, generate new keys and write them in the secure element's
persistent memory).
For information on SCP03, check the Global Platform HomePage and
google for that term [1]
[1] globalplatform.org
[2] https://github.com/OP-TEE/optee_os/
check:
core/drivers/crypto/se050/adaptors/utils/scp_config.c
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
The existing log_ret() and log_msg_ret() macros consider an error to be
less than zero. But some function may return a positive number to indicate
a different kind of failure. Add macros to check for that also.
Signed-off-by: Simon Glass <sjg@chromium.org>
When multiple log() calls are used which don't end in newline, the
log prefix is prepended multiple times in the same line. This makes the
output look strange.
Fix this by detecting when the previous log record did not end in newline.
In that case, setting a flag.
Drop the unused BUFFSIZE in the test while we are here.
As an example implementation, update log_console to check the flag and
produce the expected output.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present only a single flag (force_debug) is used in log records. Before
adding more, convert this into a bitfield, so more can be added without
using more space.
To avoid expanding the log_record struct itself (which some drivers may
wish to store in memory) reduce the line-number field to 16 bits. This
provides for up to 64K lines which should be enough for anyone.
Signed-off-by: Simon Glass <sjg@chromium.org>
As an example of an SPL test, add a new test for loading a FIT within
SPL. This runs on sandbox_spl. For this to work, the text base is adjusted
so that there is plenty of space available.
While we are here, document struct spl_load_info properly, since this is
currently ambiguous.
This test only verifies the logic path. It does not actually check that
the image is loaded correctly. It is not possible for sandbox's SPL to
actually run u-boot.img since it currently includes u-boot.bin rather than
u-boot. Further work could expand the test in that direction.
The need for this was noted at:
http://patchwork.ozlabs.org/project/uboot/patch/20201216000944.2832585-3-mr.nuke.me@gmail.com/
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this function can only locate the u-boot ELF file. For SPL it
is handy to be able to locate u-boot.img since this is what would normally
be loaded by SPL.
Add another argument to allow this to be selected.
While we are here, update the function to load SPL when running in TPL,
since that is the next stage.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present SPL only runs driver model tests. Update it to run all
available tests, i.e. in any test suite.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present each test suite has its own portion of the linker_list section
of the image, but other lists are interspersed. This makes it hard to
enumerate all the available tests without knowing the suites that each one
is in.
Place all tests together in a single contiguous list by giving them
common prefix not used elsewhere in U-Boot. This makes it possible to find
the start and end of all tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we use the linker list directly. This is not very friendly, so
add a helpful macro instead. This will also allow us to change the naming
later without updating this code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use this function instead of implementing it separately for driver model.
Make ut_run_tests() private since it is only used in test-main.c
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we use a global test state for all driver-model tests. Make use
of a local struct like we do with the other tests.
To make this work, add functions to get and set this state. When a test
starts, the state is set (so it can be used in the test). When a test
finishes, the state is unset, so it cannot be used by mistake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Driver model tests are generally run twice, once with livetree enable and
again with it disabled. Add a function to handle this and call it from the
driver model test runner.
Make ut_run_test() private since it is not used outside test-main.c now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Instead of having a separate function for running driver model tests, use
the common one. Make the pre/post-run functions private since we don't
need these outside of test-main.c
Signed-off-by: Simon Glass <sjg@chromium.org>
Move this function into test-main so that all the init is in one place.
Rename it so that its purpose is clearer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Driver model is a core part of U-Boot. We don't really need to have a
separate test structure for the driver model tests and it makes it harder
to write a test if you have to think about which type of test it is.
Subsume the fields from struct dm_test_state into struct unit_test_state
and delete the former.
Signed-off-by: Simon Glass <sjg@chromium.org>
For driver model tests we want to reinit the data structures so that
everything is in a known state before the test runs. This avoids one test
changing something that breaks a subsequent tests.
Move the call for this into test_pre_run().
Signed-off-by: Simon Glass <sjg@chromium.org>
Ultimately we want to get rid of the special driver model test init and
use test_pre_run() and test_post_run() for all tests. As a first step,
use those function to handle console recording.
For now we need a special case for setting uts->start, but that wil go
away once all init is in one place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Split out the test preparation into a separation function before
expanding it. Add a post-run function as well, currently empty.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new test runner that will eventually be able to run any test. For
now, have it run the 'command' unit tests, so that the functionality in
cmd_ut_category() moves into it.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is the main test function for driver model but not for other tests.
Rename the file and the function so this is clear.
Signed-off-by: Simon Glass <sjg@chromium.org>
The STM32MP15 boards have no reason to configure bootdelay in stm32mp1.h
as it is already done with CONFIG_BOOTDELAY (default = 2) and in
include/env_default.h.
This patch allows configuration for customers which reuse stm32mp1.h
and reduce the size of the default environment.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel
SOCFPGA SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex"
is hex formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It
combines the spl image and dtb. "u-boot-spl-dtb.hex" is needed to
generate the final configuration bitstream for Intel SOCFPGA SOC64
devices.
Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch
move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h to
*_defconfig file for both Stratix 10 and Agilex.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Carve out a function to translate a Unicode code point to an 8bit codepage.
Provide a unit test for the new function.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Now that we have switched to CONFIG_OF_CONTROL, and we can use the
env variable 'fdtcontroladdr' directly instead of creating one that
is duplicated.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The QEMU ppce500 target integrates a Freescale I2C controller and
has a Pericom pt7c4338 RTC connected to it. Enable corresponding
DM drivers so that 'date' command is actually useful.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
At present the board supports non-DM version PCI and E1000 drivers.
Switch over to use DM ETH and PCI by:
- Rewrite the PCI address map functions using DM APIs
- Enable CONFIG_MISC_INIT_R to do the PCI initialization and
address map
- Drop unnecessary ad-hoc config macros
- Remove board_eth_init() in the board codes
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The QEMU ppce500 target integrates 2 NS16550 serial ports. Switch
over to use the DM version of the driver by:
- drop unnecessary ad-hoc config macros
- add get_serial_clock() in the board codes
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This adds a basic test for the newly introduced 'addrmap' command.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[Rebase]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
At present address_map[] is static and its type is unknown to external
modules. In preparation to create a command to list its contents, this
patch moves its type definition and declaration to the header file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Remove the extern of the header because they are useless.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CONFIG_SYS_PCI_MAP_END currently points to 0xe8000000, which means
the upper end of the virtual address mapped to PCI bus address ends
at 0xe8000000. But this is wrong as the CCSBAR was already mapped
at 0xe0000000 with a 1 MiB size.
Fixes: fa08d39517 ("PPC 85xx: Add qemu-ppce500 machine")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
