Moved the pmic_max77686.c max77686_pmic.h to drivers/power
and made required changes accordingly
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The config is current broken. It compiles but does not boot because IDE is
enabled. Remove all IDE options, and enable SCSI instead.
Also add a working boot command and Linux bootargs, and enable command
line editing to make it easier to work with.
Signed-off-by: Simon Glass <sjg@chromium.org>
This allows u-boot to figure out the partitions of a chrome-os install.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
The default implementation of this function is just memset, but other
implementations will be needed when physical memory isn't accessible by
U-Boot using normal addressing mechanisms.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch fixes an issue with overlapping PCI regions
on boards with more than 64MB RAM.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch builds upon the recently introduced CBMEM console
feature of coreboot.
CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.
Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.
>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:
vvvvvvvvvvvvvvvvv
SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^
Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
When __BYTEORDER_HAS_U64__ is not defined, we got warning following:
-----
/tmp/include/linux/byteorder/little_endian.h: In function ‘__cpu_to_be64p’:
/tmp/include/linux/byteorder/little_endian.h:71:2: warning: implicit declaration of function ‘__swab64p’
[-Wimplicit-function-declaration]
-----
Usually, __arch__swab64* required for __fswab64, __swab64p and __swab64s
is defined. Therefore, __BYTEORDER_HAS_U64__ is unnecessary.
This removes __BYTEORDER_HAS_U64__.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Kim Phillips <kim.phillips@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :
#ifdef CONFIG_FSL_SATA_V2
...
#endif
To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.
This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bf
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet
connector. It is necessary to use the same base address for correct LAW
address. An offset is added for NOR flash.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning
of this virtual bank so that this bank can store RCW or be used together
with other banks to store large images.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To solve this, modify the Tegra MMC driver to use the
new bounce_buffer_*() APIs.
Note: Ideally, all U-Boot code will always provide address- and size-
aligned buffers, so a bounce buffer will only ever be needed for user-
supplied buffers (e.g. load commands). Ensuring this removes the need
for performance-sucking bounce buffer cache management and memcpy()s.
The one known exception at present is the SCR buffer in sd_change_freq(),
which is only 8 bytes long. Solving this requires enhancing struct
mmc_data to know the difference between buffer size and transferred data
size, or forcing all callers of mmc_send_cmd() to have allocated buffers
using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not
enforced in any way at present, and so cannot be assumed by the core MMC
code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The current bouncebuf API requires all parameters to be passed to both
bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf
start function to accept a state structure as a parameter, and only
require that state struct to be passed to the stop function. This
simplifies usage of the bounce buffer by clients.
Don't modify the data pointer, but rather store the temporary buffer in
this state struct. The bouncebuf code ensures that client code can
always use a single buffer pointer in the state structure, irrespective
of whether a bounce buffer actually had to be allocated.
Move cache management logic into the bounce buffer code, so that each
client doesn't have to duplicate this. I believe there's no need to
invalidate the buffer before a DMA operation, since flushing the cache
should prevent any write-backs.
Update the MXS MMC driver for this change.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
If any driver ever needs to use the bounce buffer API, it always needs
to use it. As such, providing a dummy implementation of those APIs when
CONFIG_BOUNCE_BUFFER isn't defined does not make sense. Remove the dummy
implementation.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Commits 6dc71c8 "MMC: MXS: Toggle the generic bounce buffer on the
boards" and 49a627f "MMC: Remove the MMC bounce buffer" replaced
CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER, but missed
converting a few boards over to the new option. Fix this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Bring in the code from Linux kernel.
Added to Linux kernel by:
commit e08c1694d9e2138204f2b79b73f0f159074ce2f5
Author: Andres Salomon <dilinger@queued.net>
Date: Fri Jul 4 10:00:03 2008 -0700
Some HW balks when writing both voltage setting and power up at the same
time to SDHCI_POWER_CONTROL register.
Signed-off-by: Rommel G Custodio <sessyargc@gmail.com>
CC: Andy Fleming <afleming@freescale.com>
v2: fix attribution and SOB
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch adds a NAND Flash torture feature, which is useful as a block stress
test to determine if a block is still good and reliable (or should be marked as
bad), e.g. after a write error.
This code is ported from mtd-utils' lib/libmtd.c.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: removed unnec. ifdef and unwrapped error strings]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Use a flag instead of a hard-coded macro so that sub-page reads can be
enabled in other cases (such as on-die ecc).
This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
- Sort by address, and fix column alignment
- Don't label things as localbus that aren't. Instead, put chipselect
info at the end of the description for localbus windows. Note that
NAND/NOR have their chipselects swapped when booting from NAND, and CS2
can be either PMC or VSC7385 depending on hwconfig.
- Shrink NAND to the 32K that's actually mapped in the localbus
- Assign an address and size to L2 SRAM. Remove the similarly named
but unintelligible "L2 SDRAM(REV.)".
- Remove the untrue comment about L1 stack being mapped with TLB0.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver. Some SPLs need software ECC but others can't
fit it.
All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.
Enable using of new MUSB framework on Beagle.
NOTE! This is not just a change of backend code: top-level behavior
is also changed, we now use USB device port for USB Ethernet instead
of serial.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
