Commit graph

34341 commits

Author SHA1 Message Date
Simon Glass
7b00896ade x86: ivybridge: Add a way to turn off the CAR
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
db55bd7dad x86: Commit the current MTRRs before relocation
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
aaafcd6c3f x86: ivybridge: Request MTRRs for DRAM regions
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.

We set RAM as cacheable (with write-back) and registers as non-cacheable.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:01 -08:00
Simon Glass
313aef37a1 x86: board_f: Adjust x86 boot order for performance
For bare platforms we turn off ROM-caching before calling board_init_f_r()
It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so
that the copying happens before we turn off ROM-caching.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
9818a00eea x86: ivybridge: Set up an MTRR for the video frame buffer
Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
aff2523f69 x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
3a5659f7cf x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Simon Glass
9a99caf3f3 x86: pci: Display vesa modes in hex
The hex value is more commonly understood, so use that instead of decimal.
Add a 0x prefix to avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:25:00 -08:00
Simon Glass
f4a6f0aed0 x86: Tidy up VESA mode numbers
There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:59 -08:00
Simon Glass
818f602112 x86: Use cache, don't clear the display in video BIOS
There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:59 -08:00
Simon Glass
d19ee5c27e x86: ivybridge: Only run the Video BIOS when video is enabled
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.

We could add a command to run the video BIOS later when needed, but this is
not considered at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:59 -08:00
Simon Glass
fba7eac1c8 x86: video: Add debug option to time the BIOS copy
This can be very slow - typically 80ms even on a fast machine since it uses
the SPI flash to read the data. Add an option to display the time taken.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:59 -08:00
Simon Glass
23609c71dc x86: pci: Don't return a vesa mode when there is not video
If the video has not been set up, we should not return a success code. This
can be detected by seeing if any of the variables are non-zero.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:58 -08:00
Simon Glass
6dcc815984 x86: video: Add a debug() to display the frame buffer address
Provide a way to display this address when booting.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:58 -08:00
Simon Glass
8a388085c7 x86: Correct ifdtool microcode calculation
This currently assumes that U-Boot resides at the start of ROM. Update
it to remove this assumption.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:58 -08:00
Simon Glass
6c911c4322 x86: Drop RAMTOP Kconfig
We don't need this in U-Boot since we calculate it based on available memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13 07:24:58 -08:00
Simon Glass
bbd43d659c x86: Correct XIP_ROM_SIZE
This should default to the size of the ROM for faster execution before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:58 -08:00
Bin Meng
b21b208184 x86: crownbay: Add pci devices in the dts file
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.

Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
1eb47efc49 x86: Use ePAPR defined properties for x86-uart
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
3db886a5bf serial: ns16550: Support ns16550 compatible pci uart devices
There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.

Those pci uart devices can have their register be memory-mapped, or
i/o-mapped. The driver will try to use the memory-mapped register if
the reg property in the node has an entry to describe the memory-mapped
register, otherwise i/o-mapped register will be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:24:57 -08:00
Bin Meng
a62e84d7b1 fdt: Add several apis to decode pci device node
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
2015-01-13 07:24:40 -08:00
Georgi Botev
95f5c8f226 PM9G45 adding generic board support
Signed-off-by: Georgi Botev <botev@ronetix.at>
2015-01-13 09:37:27 -05:00
Georgi Botev
ebf7bef12e PM9261 adding generic board support
Signed-off-by: Georgi Botev <botev@ronetix.at>
2015-01-13 09:37:27 -05:00
Georgi Botev
efe62a6688 PM9263 adding generic board support
Signed-off-by: Georgi Botev <botev@ronetix.at>
2015-01-13 09:37:27 -05:00
Matthias Fuchs
3c3b55d974 ppc4xx: switch VOM405 to generic board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:27 -05:00
Matthias Fuchs
348303566d ppc4xx: switch PMC405DE to generic board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:26 -05:00
Matthias Fuchs
a5ee5c6949 ppc4xx: switch PLU405 to generic board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:26 -05:00
Matthias Fuchs
37ea00929d ppc4xx: switch CPCI2DP to generic board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:26 -05:00
Matthias Fuchs
7eaeb08b20 ppc4xx: cleanup CPCI4052 board
- remove some obsolete code
- switch to generic board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:26 -05:00
Matthias Fuchs
5f1459dc0d ppc4xx: remove some CPCI405 variants
only keep CPCI4052

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:25 -05:00
Matthias Fuchs
5f8f6294a7 ppc4xx: remove G2000 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:25 -05:00
Matthias Fuchs
fc88a5bf79 ppc4xx: remove WUH405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:25 -05:00
Matthias Fuchs
807db88b62 ppc4xx: remove VOH405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:25 -05:00
Matthias Fuchs
d526330479 ppc4xx: remove PMC405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:24 -05:00
Matthias Fuchs
dbe7bb0d21 ppc4xx: remove PCI405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:24 -05:00
Matthias Fuchs
cc6e715f1b ppc4xx: remove OCRTC board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:24 -05:00
Matthias Fuchs
e434d5d729 ppc4xx: remove HUB405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:24 -05:00
Matthias Fuchs
843125daeb ppc4xx: remove HH405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:23 -05:00
Matthias Fuchs
7ac9d47a22 ppc4xx: remove DU440 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:23 -05:00
Matthias Fuchs
bc114076dc ppc4xx: remove DU405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:23 -05:00
Matthias Fuchs
9a4018e09a ppc4xx: remove DP405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:23 -05:00
Matthias Fuchs
3705726010 ppc4xx: remove CPCIISER4 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:22 -05:00
Matthias Fuchs
2404124c47 ppc4xx: remove CMS700 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:22 -05:00
Matthias Fuchs
b5e7c84f72 ppc4xx: remove ASH405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:22 -05:00
Matthias Fuchs
61b57c4ab9 ppc4xx: remove AR405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:22 -05:00
Matthias Fuchs
2b8a04e551 ppx4xx: remove APC405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13 09:37:21 -05:00
Matthias Fuchs
cbdc662a2c m68k: remove TASREG board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Stefan Roese <sr@denx.de>
2015-01-13 09:37:21 -05:00
Bin Meng
949dbc12db x86: Simplify the fsp hob access functions
Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
8f9052fd98 pci: Make pci apis usable before relocation
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.

Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00
Bin Meng
fa5530b85d x86: Support pci bus scan in the early phase
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12 17:03:41 -08:00