Commit graph

73046 commits

Author SHA1 Message Date
Tom Rini
e644dfbb17 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-15 08:10:13 -04:00
Tom Rini
8054d80b04 Merge https://source.denx.de/u-boot/custodians/u-boot-sh 2021-05-14 23:00:24 -04:00
Tom Rini
666afca0df - dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
- usb: dwc3-meson-g12a: skip phy on -ENODATA aswell
 - net: dwmac_meson8b: do not set TX delay in TXID & RXID
 - net: designware: meson8b: add g12a compatible
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Merge tag 'u-boot-amlogic-20210514' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
- usb: dwc3-meson-g12a: skip phy on -ENODATA aswell
- net: dwmac_meson8b: do not set TX delay in TXID & RXID
- net: designware: meson8b: add g12a compatible
2021-05-14 22:59:59 -04:00
Tom Rini
579e07501a Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2021-05-14 22:59:48 -04:00
Neil Armstrong
4c2eb955cf net: designware: meson8b: add g12a compatible
Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14 17:46:50 +02:00
Neil Armstrong
81d0edafd9 net: dwmac_meson8b: do not set TX delay in TXID & RXID
When the PHY interface is set as TXID & RXID, the delays should be taken from DT,
but first they should not be hardcoded since the PHY driver will set them.

Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-14 17:43:09 +02:00
Neil Armstrong
60e531fabf usb: dwc3-meson-g12a: skip phy on -ENODATA aswell
If the PHY isn't specified in the DT, -ENODATA means it should be skipped,
handle it like -ENOENT.

With that, devices without USB3 supported can have USB working (Odroid-HC4).

Fixes: adb049abf7 ("usb: dwc3: Add Meson G12A USB Glue")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14 17:41:12 +02:00
Neil Armstrong
d39620e045 ARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
This lacks the right u-boot specific DT include to make HDMI work.

Reported-by: B1oHazard <ty3uk@mail.ua>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-05-14 17:41:11 +02:00
Bin Meng
ffdc71bc09 Revert "riscv: cpu: fu740: clear feature disable CSR"
This reverts commit bc8bbb77f7.

This commit breaks U-Boot booting on SiFive Unleashed board, as
there is no such CSR on U54 core.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-05-14 16:26:20 +08:00
Vincent Chen
cc25f346c9 pwm: sifive: make set_config() and set_enable() work properly
The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work
properly due to the wrong implementations. It will cause the u-boot
PWM command to not work as expected. The bugs will be resolved in this
patch.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-14 16:25:42 +08:00
Sean Anderson
81dadfa4bc riscv: Don't reserve AI ram in k210 dts
It is no longer necessary to disallow ai ram, since it is enabled by the
sram driver.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:50 +08:00
Sean Anderson
2111f4e8bf riscv: k210: Use AI as the parent clock of aisram, not PLL1
Testing showed that disabling AI while leaving PLL1 enabled disabled the
aisram. This suggests that AI is a more appropriate clock for that ram
bank.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:49 +08:00
Sean Anderson
2d64e3829b riscv: k210: Rename airam to aisram
This is more consistent with the naming of other ram banks, and matches
what Linux is doing.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:49 +08:00
Sean Anderson
23058052de riscv: Enable AI ram on K210
We just need to initialize all the clocks pre-reloc. The clock driver
creates a bunch of devices, so we need to increase the pre-reloc malloc
arena.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:49 +08:00
Sean Anderson
2eebe5b373 riscv: Enable some devices pre-relocation
These devices are necessary for the clock driver, which is required by the
sram driver, to run pre-relocation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:48 +08:00
Sean Anderson
09ad08fa1a clk: Add support for the k210 clock driver pre-relocation
Variables which had previously been stored in .bss are moved to .data. In
addition, probed needs to be reset when the clock driver is re-bound
post-relocation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:48 +08:00
Sean Anderson
800c7f6a1f clk: k210: Move the clint clock to under aclk
No other (real) clocks have the cpu clock as their parent; instead they are
children of aclk. Move the clint clock under aclk to match them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:48 +08:00
Sean Anderson
f93ce98eb2 clk: k210: Remove k210_register_pll
This simplifies the PLL creation process, since we don't have to pass all
the parameters individually.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:48 +08:00
Sean Anderson
598a06dcb4 clk: k210: Fix PLL enable always getting taken
This conditional always evaluated as false, regardless of the value of reg.
Fix it so that it properly tests the bits in the PLL register. Also test
PLL_EN, now that we set it.

Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:47 +08:00
Sean Anderson
d0686a02b9 clk: k210: Fix PLLs not being enabled
After starting or setting the rate of a PLL, the enable bit must be set.

This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
2021-05-14 16:20:47 +08:00
Sean Anderson
8c12cb3fd8 clk: Warn on failure to assign rate
If the user/dev explicitly requests a clock be assigned a certain rate,
then we should warn them if we can't do it. This makes it clear if the
clock is running at the default rate.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14 16:20:47 +08:00
Rick Chen
c0c80e7843 MAINTAINERS: Add a co-maintainer for RISC-V
Add Leo as co-maintainer for RISC-V.

Signed-off-by: Rick Chen <rick@andestech.com>
2021-05-14 16:19:48 +08:00
Tom Rini
530c8d4af2 Merge branch '2021-05-13-extension-board-detection-and-DT-overlay-application'
- Improve support for various forms of extension boards and add DT
  overlay application support.
2021-05-13 13:09:14 -04:00
Kory Maincent
1569847e7c am335x: add support for cape detect functionality
Update the Kconfig and the board file to make the am335x board compatible
with cape detection.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
d705527a89 arm: am335x: add support for i2c2 bus
The am335x from BeagleBone use i2c EEPROM to detect capes.
The memory is wired to i2c bus 2 therefore it need to be enabled.

Add i2c2 clock, pinmux description and pinmux enable function.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
77115a5526 configs: CHIP: add support for DIP detect functionality
This commit enables using the extension board detection mechanism on
CHIP boards

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Andre Przywara <andre.przywara@arm.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
6c2c7e9cb9 arm: sunxi: add support for DIP detection to CHIP board
Add the extension_board_scan specific function to scan the information
of the EEPROM on one-wire and fill the extension struct.
Add the Kconfig symbol to enable the needs to detect DIPs.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Andre Przywara <andre.przywara@arm.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
c9dffc9719 w1: replace dt detection by automatic detection
This patch changes the functioning of the detection of w1 devices.
The old way was a comparison between detected w1 and the ones described in
the device tree. Now it will just look for the driver matching the family
id of the w1 detected.

The patch is inspired from Maxime Ripard code.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-13 13:09:09 -04:00
Kory Maincent
0705e25cd0 am57xx: add support for cape detect functionality
This commit enables using the extension board detection mechanism on
AM57xx based platforms.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
8c1d443206 ti/common: add support for extension_scan_board function
The BeagleBone platforms all use a common mechanism to discover and
identify extension boards (called "capes"): each extension board has an
I2C-connected EEPROM describing itself.

This patch implements a generic extension_scan_board() feature that can
be used by all BeagleBone platforms to read those I2C EEPROMs and fill
in the list of "extension" structures.

Following commits will enable this common logic on two BeagleBone
platforms.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
95300f203f pytest: add sandbox test for "extension" command
This commit extends the sandbox to implement a dummy
extension_board_scan() function and enables the extension command in
the sandbox configuration. It then adds a test that checks the proper
functionality of the extension command by applying two Device Tree
overlays to the sandbox Device Tree.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
[trini: Limit to running on sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-13 13:09:09 -04:00
Kory Maincent
2f84e9cf06 cmd: add support for a new "extension" command
This patch adds a new "extension" command, which aims at detecting
extension boards connected to the hardware platform, and apply the
Device Tree overlays that describe the hardware present on those
extension boards.

In order to enable this mechanism, board-specific code must implement
the extension_board_scan() function that fills in a linked list of
"struct extension", each describing one extension board. In addition,
the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig
boolean.

Based on this:

 - "extension scan" makes the generic code call the board-specific
   extension_board_scan() function to retrieve the list of detected
   extension boards.

 - "extension list" allows to list the detected extension boards.

 - "extension apply <number>|all" allows to apply the Device Tree
   overlay(s) corresponding to one, or all, extension boards

The latter requires two environment variables to exist and set one variable
to run:

 - extension_overlay_addr: the RAM address where to load the Device
   Tree overlays

 - extension_overlay_cmd: the U-Boot command to load one overlay.
   Indeed, the location and mechanism to load DT overlays is very setup
   specific.

 - extension_overlay_name: set by the command: the name of the DT which
   will be load during the execution.

When calling the command described in the extension_overlay_cmd
variable, the variable extension_overlay_name will be defined. So a
typical extension_overlay_cmd will look like this:

  extension_overlay_cmd=load mmc 0:1 $extension_overlay_addr /boot/$extension_overlay_name

Here is an example on how to use it:
=> run loadfdt
=> fdt addr $fdtaddr
=> setenv extension_overlay_addr 0x1000
=> setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}'
=> extension scan
Found 1 extension board(s).
=> extension apply 0
519 bytes read in 3 ms (168.9 KiB/s)

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-13 13:09:05 -04:00
Kory Maincent
bbdbcaf59d fdt_support: move fdt_valid from cmd_fdt.c to fdt_support.c
Move the fdt_valid function to fdt_support.
This changes allow to be able to test the validity of a devicetree in
other c files.

Update code syntax.

Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Maxime Ripard <maxime@cerno.tech>
2021-05-13 07:19:34 -04:00
Marek Vasut
8f76c9d73a ARM: renesas: Scrub duplicate memory nodes from DT on Gen3
Scrub duplicate /memory@* node entries here. Some R-Car DTs might
contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
either generates single /memory node or updates the first /memory
node. Any remaining memory nodes are thus potential duplicates.

However, it is not possible to delete all the memory nodes right
away, since some of those might not be DRAM memory nodes, but some
sort of other memory. Thus, delete only the memory nodes which are
in the R-Car3 DBSC ranges.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-12 21:36:27 +02:00
Marek Vasut
bd83431ea3 ARM: rmobile: Add missing rcar-common/common.c to Beacon RZG2M kit
The rcar-common/common.c contains various common board functions shared
by all R-Car and RZG boards. This board is not compiling the file in, so
add it. This way, part of the board code can be de-duplicated too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
2021-05-12 21:36:27 +02:00
Tom Rini
ea184cbff9 Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver
2021-05-12 10:07:21 -04:00
Vignesh Raghavendra
bbc9da58b3 ARM: dts: k3-am642-sk: Add ethernet related DT nodes
Add CPSW related nodes for AM642 SK. There are two CPSW ports on the
board but U-Boot supports only the first port.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:39 +05:30
Vignesh Raghavendra
bc17fccbd0 ARM: dts: k3-am64-main: Add CPSW DT nodes
AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same
(based on kernel DT).

Disable second port as its by default set to ICSS usage on EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:39 +05:30
Vignesh Raghavendra
845e1060d3 net: ti: am65-cpsw-nuss: Add a new compatible for AM64
Add a new compatible to support AM64 SoC

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:39 +05:30
Vignesh Raghavendra
2411e85b99 net: ti: am65-cpsw-nuss: Don't cache disabled port ID
Currently driver may end up caching disabled port ID as active
interface. Fix this by bailing out earlier in case port is marked
disabled in the DT.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
8441d49e60 net: ti: am65-cpsw-nuss: Prepare to support non primary ext port
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8)
Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port)
as preparation to allow any one of the 8 ports to be used as ethernet
interface in U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
9a92851c33 dma: ti: k3-udma: Add BCDMA and PKTDMA support
Sync BCDMA and PKTDMA support from Kernel for AM64 SoC

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
6f617d8618 dma: ti: k3-psil-am64: Add AM64 PSIL endpoint data
Add AM64 SoC specific channel mapping and endpoint data.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
b00030e267 dma: ti: k3-psil: Extend PSIL EP data extension for AM64
Extend PSIL EP data to include AM64 DMA specific information

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
035c679a77 dma: ti: k3-psil-am654: Drop unused PSIL EP static data
ICSSG Ethernet driver uses two src threads per port (one per slice).
Similarly CPSW uses one src thread.

Drop PSIL EP static data for other src threads in order to reduce
R5 SPL footprint. This makes AM65x board bootable again.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
f1e97c7058 soc: ti: k3-navss-ringacc: Remove unused ring modes
With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed
ring mode, all other K3 SoCs have also been moved to this common
baseline. Therefore drop other modes such as
K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint.

There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
c409b4932d soc: ti: k3-navss-ringacc: Add AM64 ringacc support
AM64 dual mode rings are modeled as pair of Rings objects which has common
configuration and memory buffer, but separate real-time control register
sets for each direction mem2dev (forward) and dev2mem (reverse).

AM64 rings must be requested only using k3_ringacc_request_rings_pair(),
and forward ring must always be initialized/configured. After this any
other Ringacc APIs can be used without any callers changes.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
91f1e792fe firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest
Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support
AM64x BCDMA Block copy channels.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Vignesh Raghavendra
ec658e7ee5 board: ti: am64x: Parse MAC address from board EEPROM
Parse MAC addresses from EEPROM and set them in the env. This is needed
to get MAC address for additional ethernet ports on the EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12 16:36:38 +05:30
Lokesh Vutla
e0e5374b91 configs: am64x_evm_a53: Enable support for building multiple dtbs
Enable all relevant configs for building multiple dtbs into a single fit
image and load the right dtb for next stage.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:36:38 +05:30