Commit graph

25520 commits

Author SHA1 Message Date
Peng Fan
152adee1b6 imx:mx6sxsabresd: change CONFIG_SYS_FSL_ESDHC_ADDR
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR which is used
in board_mmc_init.

If board_mmc_init failed, cpu_mmc_init->fsl_esdhc_mmc_init will use
CONFIG_SYS_FSL_ESDHC_ADDR to initialize sdhc. So set this macro to
correct value.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2014-09-16 13:33:46 +02:00
Stefan Agner
d6d07a9bec arm: vf610: add NAND support for vf610twr
This adds NAND support for the Vybrid tower system (TWR-VF65GS10)
provided by the vf610_nfc driver. Full 16-Bit bus width is
supported. Also an aditional config vf610twr_nand is introduced
which gets the environment from NAND. However, booting U-Boot from
NAND is not yet possible due to missing boot configuration block
(BCB).

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-16 13:25:45 +02:00
Stefan Agner
72d7beabf7 mtd: nand: add Freescale vf610_nfc driver
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
The driver is called vf610_nfc since this is the first supported
and tested hardware platform supported by the driver.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
2014-09-16 13:25:18 +02:00
Andrew Ruder
816264fc66 arm: mx35: use common timer functions
This patch moves mx35 to the common timer functions added in commit

  8dfafdd - Introduce common timer functions <Rob Herring>

The (removed) mx35 timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks().  get_ticks() returned a 32-bit value
cast up to a 64-bit value.  If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locks the processor.  Rather than patch the specific mx35 issues, simply
move everything over to the common code.

Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-09-16 12:53:09 +02:00
Andrew Ruder
93a0ea501e arm: mx31: use common timer functions
This patch moves mx31 to the common timer functions added in commit

  8dfafdd - Introduce common timer functions <Rob Herring>

The (removed) mx31 timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks().  get_ticks() returned a 32-bit value
cast up to a 64-bit value.  If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locks the processor.  Rather than patch the specific mx31 issues, simply
move everything over to the common code.

Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Helmut Raiger <helmut.raiger@hale.at>
2014-09-16 12:51:46 +02:00
Ye.Li
4c97f16911 imx: mx6slevk: Change to use generic board
Enable CONFIG_SYS_GENERIC_BOARD for imx6slevk to use generic board.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-11 11:04:26 +02:00
Ye.Li
9500fac7ea imx: mx6q/dlarm2: Change to use generic board
Enable the CONFIG_SYS_GENERIC_BOARD for imx6q/dl arm2 board to
use generic board.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-11 11:02:39 +02:00
Fabio Estevam
6ce79d2f32 README.imximage: Fix the maximum DCD size
In commit 021e79c853 ("tools: imximage: Fix the maximum DCD size for
mx53/mx6") we have fixed the maximum DCD size for mx53/mx53.

Do the same on the README document for consistency.

Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-09-11 10:14:04 +02:00
Stefano Babic
3d8f1798ba imx: Fix build of mx6sxsabresd
Commit 224beb833e add clock
enabling function for FEC, but the masks are not available
for SX processor and the mx6sxsabresd cannot be built clean.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-11 10:13:44 +02:00
Fabio Estevam
c860eed176 mx6sxsabresd: Add PCI support
Tested with an Intel Wireless PCI 7260HMW card:

U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: WDOG
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
  00:01.0     - 16c3:abcd - Bridge device
   01:00.0    - 8086:08b1 - Network controller

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-09-09 17:24:49 +02:00
Fabio Estevam
1b8ad74a6f pcie_imx: Add mx6solox support
Let PCI on mx6solox also be supported.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 17:24:49 +02:00
Fabio Estevam
ac17dcf653 mx6: imx-regs: Provide a structure for GPC registers
Introduce a structure for accessing the General Power Controller block (GPC)
registers.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-09-09 17:24:49 +02:00
Fabio Estevam
19a895cbe9 mx6qsabreauto: Remove imx6q-sabreauto.dts
Commit fa9c021632 ("mx6: add example DTB for mx6qsabreauto") introduced
'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains
the 'model' and 'compatible' strings.

After this commit the final binary is also changed from 'u-boot.imx' to
'u-boot-dtb.imx', which may confuse users.

So revert it until a more complete and useful device tree could be provided.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2014-09-09 17:11:01 +02:00
Guillaume GARDET
3ee96c7da9 imx: nitrogen6x: Replace 'fatload' by 'load' command in env settings to be filesystem independent
nitrogen6x.h file defines CONFIG_CMD_FS_GENERIC, so we are able to use generic
'load' command instead of 'fatload'. It allows to use ext filesystem and keep
compatibilty with fat filesystem.

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Stefano Babic <sbabic@denx.de>
Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
2014-09-09 16:58:06 +02:00
Fabio Estevam
f4fb5ef045 mx6dlsabresd: Use its own DCD table
Currently mx6dlsabresd shares the same DCD settings with the nitrogen board.

Provide a DCD configuration file specific to mx6dlsabresd with the settings
recommended by the Freescale hardware team.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-09-09 16:55:22 +02:00
Stefan Agner
89e69fd4a9 arm: vf610: lpuart: disable FIFO on initializaton
UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.

This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-09 16:54:16 +02:00
Stefan Agner
a3db78d887 arm: vf610: lpuart: fix status register handling
The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.

Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.

Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-09 16:52:44 +02:00
Nikolay Dimitrov
2d59e3ecd2 mx6: Fix ECSPI typo in soc_boot_modes
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2014-09-09 16:47:43 +02:00
Ye.Li
03ea24b2a9 imximage: Fix imximage IVT bug for EIM-NOR boot
The load region size of EIM-NOR are defined to 0. For this case,
the parameter "imximage_init_loadsize" must be calculated.
The imximage tool implements the calculation in the "imximage_generate"
function, but the following function "imximage_set_header" resets the value
and not calculate. This bug cause some fields of IVT head are not
correct, for example the boot_data and DCD overlay the application area.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-09 16:39:02 +02:00
Ye.Li
4aa7ac30a7 iMX6: Disable the L2 before chaning the PL310 latency
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.

Signed-off-by: Ye.Li <Ye.Li@freescale.com>
2014-09-09 16:30:40 +02:00
Thierry Reding
dc73cbe7b0 imx: ventana: Avoid undefined behaviour
The leds array within struct ventana has space for 3 elements, but the
setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent
versions of GCC complain about that:

	board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio':
	board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations]
	   if (gpio_cfg[board].leds[i])
				   ^
	board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop
	  for (i = 0; i < 4; i++) {
	  ^

Fix this by making the upper bound of the loop match the array size.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 16:26:33 +02:00
Fabio Estevam
021e79c853 tools: imximage: Fix the maximum DCD size for mx53/mx6
According to mx53 and mx6 reference manuals:

"The maximum size of the DCD limited to 1768 bytes."

As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and
excluding the first entry, which is the header leads to 220 as the maximum
number for DCD size.

Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Nitin Garg <nitin.garg@freescale.com>
2014-09-09 16:23:00 +02:00
Tim Harvey
dad08286ea imx: ventana: add pci fixup for PLX PEX860x switch GPIO
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion.
These boards use GPIO on the PLX device as PERST# for the downstream ports
thus we assert this when the PLX is enumerated.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 16:15:03 +02:00
Tim Harvey
0991866cf7 pci: add support for board_pci_fixup_dev function
Some board-level drivers may wish to have per-device fixup functions
for PCI devices.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 16:15:02 +02:00
Nikita Kiryanov
206f38f727 arm: mx6: cm_fx6: add sata support
Add support for SATA.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:37:08 +02:00
Nikita Kiryanov
f66113c0ef arm: mx6: cm_fx6: use eeprom
Use Compulab eeprom module to obtain revision number, serial number, and
mac address from the EEPROM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:37:08 +02:00
Nikita Kiryanov
f42b2f6061 arm: mx6: cm_fx6: add i2c support
Add support for all 3 I2C busses on Compulab CM-FX6 CoM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:37:08 +02:00
Nikita Kiryanov
0f3effb99f arm: mx6: cm_fx6: add usb support
Add USB and USB OTG host support for Compulab CM-FX6 CoM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:37:08 +02:00
Nikita Kiryanov
02b1343e4a arm: mx6: cm_fx6: add ethernet support
Add ethernet support for Compulab CM-FX6 CoM

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:37:08 +02:00
Nikita Kiryanov
a6b0652bb5 arm: mx6: cm_fx6: add nand support
Add NAND support for Compulab CM-FX6 CoM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:37:07 +02:00
Nikita Kiryanov
e32028a70b arm: mx6: add support for Compulab cm-fx6 CoM
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:35:43 +02:00
Nikita Kiryanov
ea818ae748 arm: mx6: add get_cpu_type()
Define get_cpu_type(). Reuse it in is_cpu_type().

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:35:00 +02:00
Nikita Kiryanov
07ee927d2c arm: mx6: ddr: fix cs0_end calculation
Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.

This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.

Refactor the calculation.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:35:00 +02:00
Nikita Kiryanov
08155289a4 arm: mx6: ddr: configure MMDC for slow_pd
According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).

Configure MMDC for slow pd.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 15:35:00 +02:00
Nikita Kiryanov
06a51b8cc8 arm: mx6: ddr: do not write into reserved bit
Bit 16 in mapsr register is in a reserved field. Don't write to it.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:35:00 +02:00
Nikita Kiryanov
3368918f71 arm: mx6: ddr: cleanup
No functional changes.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:33:39 +02:00
Nikita Kiryanov
c6c2492ad8 i2c: imx: add macros to setup pads for multiple SoC types
Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:32:32 +02:00
Nikita Kiryanov
dc383dd583 sata: dwc_ahsata: implement sata_port_status
Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:32:32 +02:00
Nikita Kiryanov
52658fda7a compulab: eeprom: add support for defining eeprom i2c bus
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM
module what I2C bus the EEPROM is located at. Make cl_eeprom_read()
switch to that bus when reading EEPROM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Dmitry Lifshitz <lifshitz@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:32:32 +02:00
Nikita Kiryanov
224beb833e mx6: add clock enabling functions
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:32:32 +02:00
Tim Harvey
a7c67d7c49 imx: ventana: added cputype env var
There are many similarities between the IMX6QUAD/IMX6DUAL and there are
many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env
variable that tells you which type you have.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 15:19:03 +02:00
Tim Harvey
3aa226740f imx: ventana: add GW5520 support
The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as:
 * 2x MiniPCIe sockets
 * 2x USB host sockets
 * 2x i210 GigE
 * HDMI out
 * digital I/O expansion

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 15:13:25 +02:00
Tim Harvey
c91e4b8b08 imx: ventana: base SPL MMDC calibration on width and size not board
The IMX6 MMDC calibration registers depend on propagation delay and capacitive
loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the
board layout varies little in trace-lengths such that propagation delays are
irrelevant thus we can simply things by using calibration values obtained
from various board layouts based on a common SoC and DDR chip configuration.

This eliminates board-model from being needed allowing more flexibility. These
values were tested on a large sample size of Gateworks Ventana boards ranging
in layout, and memory configuration over the entire temperature range supported.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 15:13:25 +02:00
Tim Harvey
5b94b6f6b2 imx: ventana: updated notes regarding NAND boot errata
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 15:13:24 +02:00
Fabio Estevam
f599288d55 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.

As explained by Ye Li:

"The TDAR bit is cleared when the descriptors are all out from TX ring, but on
mx6solox we noticed that the READY bit is still not cleared right after TDAR.
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared.
In mx6solox, we use a later version of FEC IP. It looks like that this
intrinsic behaviour of TDAR bit has changed in this newer FEC version."

Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.

No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 15:06:12 +02:00
Fabio Estevam
db5b7f566e net: fec_mxc: Adjust RX DMA alignment for mx6solox
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.

Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs from mx6solox and also works for the other SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 15:05:37 +02:00
Albert ARIBAUD
a6bc0195db Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-09-09 09:19:10 +02:00
Albert ARIBAUD
b653516769 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-09-09 00:21:24 +02:00
Ajay Kumar
5cecf21fb1 CONFIGS: peach-pit: Enable display for peach_pit board
Enable drivers for FIMD, DP and parade bridge chip.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:08 +09:00
Ajay Kumar
466d40396e ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00