We move the existing CONFIG_POST_* functionality over to CFG_POST and
then introduce CONFIG_POST to Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig,
e.g. hwconfig=fsl_ddr:parity=on.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Documentation fix to README.fsl-ddr to fix typos and
to reflect use of 'd' hotkey to enter the FSL DDR debugger.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add copy command which allows copying of DIMM/controller settings.
This saves tedious retyping of parameters for each identical DIMM
or controller.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Using environmental variable "ddr_interactive" to activate interactive DDR
debugging seomtiems is not enough. For example, after updating SPD with a
valid but wrong image, u-boot won't come up due to wrong DDR configuration.
By enabling key press method, we can enter debug mode to have a chance to
boot without using other tools to recover the board.
CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the
debug mode by key press, press key 'd' shortly after reset, like one would
do to abort auto booting. It is fixed to lower case 'd' at this moment.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.
Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Interactive DDR debugging provides a user interface to view and modify SPD,
DIMM parameters, board options and DDR controller registers before DDR is
initialized. With this feature, developers can fine-tune DDR for board
bringup and other debugging without frequently having to reprogram the flash.
To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
file and set an environment variable to activate it. Syntax:
setenv ddr_interactive on
After reset, U-boot prompts before initializing DDR controllers
FSL DDR>
The available commands are
print print SPD and intermediate computed data
reset reboot machine
recompute reload SPD and options to default and recompute regs
edit modify spd, parameter, or option
compute recompute registers from current next_step to end
next_step shows current next_step
help this message
go program the memory controller and continue with u-boot
The first command should be "compute", which reads data from DIMM SPDs and
board options, performs the calculation then stops before setting DDR
controller. A user can use "print" and "edit" commands to view and modify
anything. "Go" picks up from current step with any modification and
compltes the calculation then enables the DDR controller to continue u-boot.
"Recompute" does it over from fresh reading.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
DDR2 has different ODT table and values. Adding table according to Samsung
application note.
Fix additive latency calculation to avoid interger underflow.
Also converted typedef dynamic_odt_t to struct dynamic_odt.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.
Enable address parity and RCW by default for RDIMMs.
Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.
Use a formula to calculate rodt_on for timing_cfg_5.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
ECC can be turned on/off by this switch. If this switch is omitted, it is ON by
default.
Updated hwconfig calls to use local buffer.
Syntax is
hwconfig=fsl_ddr:ecc=on
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The memory test is performed after DDR initialization when U-boot stills runs
in flash and cache. On recent mpc85xx platforms, the total memory can be more
than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a
sliding TLB window. After the testing, DDR is remapped with up to 2GB memory
from the lowest address as normal.
If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for
further debugging.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.
Also check dimm size and rank size for memory controller interleaving
Signed-off-by: York Sun <yorksun@freescale.com>
Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with
hwconfig parameters. The syntax is
setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>"
The mode values for memory controller interleaving are
cacheline
page
bank
superbank
The mode values for bank interleaving are
cs0_cs1
cs2_cs3
cs0_cs1_and_cs2_cs3
cs0_cs1_cs2_cs3
Signed-off-by: York Sun <yorksun@freescale.com>
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
