Commit graph

69573 commits

Author SHA1 Message Date
Ilias Apalodimas
6974a4a373 charset: make u16_strnlen accessible at runtime
commit 1fabfeef506c ("efi_loader: parameter check in GetNextVariableName()")
introduces a check using u16_strnlen(). This code is used on EFI
runtime variables as well, so unless we mark it as runtime, the kernel
will crash trying to access it.

Fixes: 1fabfeef506c ("efi_loader: parameter check in GetNextVariableName()")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-11-29 05:18:37 +01:00
Etienne Carriere
03699bc756 lib/efi_loader: fix ABI in efi_mm_communicate_header
Pack struct efi_mm_communicate_header as done in EDK2 as seen in
release 201808 [1]. If not packed sizeof() for the structure adds
4 additional bytes on 32bit targets which breaks the ABI.

Link: [1] https://github.com/tianocore/edk2/blob/edk2-stable201808/MdePkg/Include/Protocol/MmCommunication.h#L21
Fixes: 23a397d2e2 ("efi_loader: Add headers for EDK2 StandAloneMM communication")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2020-11-29 05:18:37 +01:00
Heinrich Schuchardt
31cadc3635 efi_loader: enable EFI_SET_TIME on sandbox and QEMU ARM
Enable EFI_SET_TIME on the sandbox and QEMU ARM to ensure that we compile
and test the relevant code.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-11-29 05:18:37 +01:00
Heinrich Schuchardt
1ec29aa306 fs: fat: use ATTR_ARCH instead of anonymous 0x20
Using constants instead of anonymous numbers increases code readability.

Fixes: 704df6aa0a ("fs: fat: refactor write interface for a file offset")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-11-29 05:18:16 +01:00
Heinrich Schuchardt
a2c5a92d48 fs: fat: directory entries starting with 0x05
0x05 is used as replacement letter for 0xe5 at the first position of short
file names. We must not skip over directory entries starting with 0x05.

Cf. Microsoft FAT Specification, August 30 2005

Fixes: 39606d462c ("fs: fat: handle deleted directory entries correctly")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-11-29 05:18:16 +01:00
Heinrich Schuchardt
661d223868 fs: fat: avoid NULL dereference when root dir is full
When trying to create a file in the full root directory of a FAT32
filesystem a NULL dereference can be observed.

When the root directory of a FAT16 filesystem is full fill_dir_slot() must
return -1 to signal that a new directory entry could not be allocated.

Fixes: cd2d727fff ("fs: fat: allocate a new cluster for root directory of fat32")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-11-29 05:18:16 +01:00
Tom Rini
f6cf78dc6a Merge https://gitlab.denx.de/u-boot/custodians/u-boot-i2c 2020-11-28 10:55:46 -05:00
Pragnesh Patel
f517e5fe98 riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller
Enable support for SiFive FU540 Opencores I2C master controller.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-11-28 08:30:41 +01:00
Pragnesh Patel
b2d4cbe6d4 i2c: ocores: add i2c driver for OpenCores I2C controller
Add support for the OpenCores I2C controller IP core
(See http://www.opencores.org/projects.cgi/web/i2c/overview).

This driver implementation is inspired from the Linux OpenCores
I2C driver available.

Thanks to Peter Korsgaard <peter@korsgaard.com> for writing Linux
OpenCores I2C driver.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-11-28 08:30:41 +01:00
Simon Glass
942012246a i2c: designware_i2c: Don't warn if no reset controller
At present if CONFIG_RESET is not enabled, this code shows a warning:

  designware_i2c_ofdata_to_platdata() i2c_designware_pci i2c2@16,0:
	Can't get reset: -524

Avoid this by checking if reset is supported, first.

Fixes: 622597dee4 ("i2c: designware: add reset ctrl to driver")
Signed-off-by: Simon Glass <sjg@chromium.org>
2020-11-28 08:30:41 +01:00
Baruch Siach
5a13c0d134 i2c: mvtwsi: disable i2c slave also on Armada 8k
The hidden I2C slave is also present on the Armada 8k AP806. Testing
shows that this I2C slave causes the same issues as Armada 38x.
Disabling that I2C slave fixes all these issues.

I2C blocks on the Armada 8k CP110 are not affected.

Extend the I2C slave disable to Armada 8k as well.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-11-28 08:17:16 +01:00
Jaehoon Chung
b3dc016caa mmc: check a return value about regulator's always-on
Regulator can be set to "always-on".
It's not error about enable/disable. It needs to check about
its condition.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-11-28 10:44:39 +08:00
Jaehoon Chung
58896458b7 mmc: display an error number to debug
It's useful to know an error number when it's debugging.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-11-28 10:43:42 +08:00
Yangbo Lu
8ee802f899 mmc: fsl_esdhc: make sure delay chain locked for HS400
For eMMC HS400 mode, the DLL reset is a required step for mmc rescan.
This step has not been documented in reference manual, but the RM will
be fixed sooner or later.

In previous commit to support eMMC HS400,
  db8f936 mmc: fsl_esdhc: support eMMC HS400 mode

the steps to configure DLL could be found in commit message,
  13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
  14. Wait for delay chain to lock.

these would be fixed as,
  13.   Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
  13.1  Write DLLCFG0[DLL_RESET] to 1 and wait for 1us,
        then write DLLCFG0[DLL_RESET]
  14.   Wait for delay chain to lock.

This patch is to add the step of DLL reset, and make sure delay chain
locked for HS400.

Fixes: db8f93672b ("mmc: fsl_esdhc: support eMMC HS400 mode")
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28 10:39:44 +08:00
Yangbo Lu
263ddfc345 mmc: fsl_esdhc: set sysctl register for clock initialization
The initial clock setting should be through sysctl register only,
while the mmc_set_clock() will call mmc_set_ios() introduce other
configurations like bus width, mode, and so on.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28 10:39:44 +08:00
Sean Anderson
da12917060 mmc: Add some helper functions for retrying on error
All of the existing quirks add retries to various calls of mmc_send_cmd.
mmc_send_cmd_quirks is a helper function to do this retrying behavior. It
checks if quirks mode is enabled, and if a specific quirk is activated it
retries on error.

This also adds mmc_send_cmd_retry, which retries on error every time
(instead of if a quirk is activated).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-28 10:39:44 +08:00
Tom Rini
7889951d0f - STM32 MCU's DT update
- Add DHCOM based STM32MP15x PicoITX board
 - Correct ALIGN macro usage for on syram for SPL dcache support
 - Fixes on DHCOM: uSD card-detect GPIO and Drop QSPI CS2
 - Fix compilation issue for spl_mmc_boot_partition
 - Fix MTD partitions for serial boot
 - Add support of MCU HOLD BOOT with reset for stm32 remoteproc
   (prepare alligneent with  kernel DT)
 - Correct bias information and support in STM32 soc and STMFX
 - Support optional vbus in usbphyc
 - Update FIT examples to avoid kernel zImage relocation before decompression
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Merge tag 'u-boot-stm32-20201125' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- STM32 MCU's DT update
- Add DHCOM based STM32MP15x PicoITX board
- Correct ALIGN macro usage for on syram for SPL dcache support
- Fixes on DHCOM: uSD card-detect GPIO and Drop QSPI CS2
- Fix compilation issue for spl_mmc_boot_partition
- Fix MTD partitions for serial boot
- Add support of MCU HOLD BOOT with reset for stm32 remoteproc
  (prepare alligneent with  kernel DT)
- Correct bias information and support in STM32 soc and STMFX
- Support optional vbus in usbphyc
- Update FIT examples to avoid kernel zImage relocation before decompression
2020-11-25 11:00:52 -05:00
Patrick Delaunay
60a2dd6aa2 board: st: stm32mp1: update load address for FIT examples
Update kernel load address for FIT examples to avoid relocation:
- Kernel example uses Image.gz with U-Boot gzip decompression
  at final kernel location 0x0xC0008000.
- Copro example loads zImage at a correct location (0xC4000000),
  to avoid zImage relocation before decompression by kernel code.

An other solution to avoid zImage relocation is to align
the kernel load and entry address with the real location in FIT
(the relocation of zImage is skipped in U-Boot bootm command for
identical address) but it is less flexible because this offset
depends on FIT content:

For example:

## Loading kernel from FIT Image at c2000000 ...
   Using 'ev1' configuration
   Trying 'kernel' kernel subimage
     Description:  Linux kernel
     Created:      2020-10-22   9:08:32 UTC
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0xc20000cc

The kernel offset in FIT is 0xCC in FIT and zImage is decompressed at
0xC0008000 by kernel code:

kernel {
	description = "Linux kernel";
	data = /incbin/("zImage");
	type = "kernel";
	arch = "arm";
	os = "linux";
	compression = "none";
	load = <0xC20000cc>;
	entry = <0xC20000cc>;
	hash-1 {
		algo = "sha1";
	};
};

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 14:27:19 +01:00
Patrick Delaunay
c480138958 phy: stm32: usbphyc: manage optional vbus regulator on phy_power_on/off
This patch adds support for optional vbus regulator.
It is managed on phy_power_on/off calls and may be needed for host mode.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 12:02:58 +01:00
Patrick Delaunay
e27e96aa80 pinctrl: stmfx: update pin name
Update pin name to avoid duplicated name with SOC GPIO
gpio0...gpio15 / agpio0....agpio7: add a stmfx prefix.

This pin name can be used in pinmux command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 12:01:53 +01:00
Patrick Delaunay
c2a8181d45 pinctrl: stmfx: update pincontrol and gpio device name
The device name is used in pinmux command and in log trace
so it is better to use the parent parent name ("stmfx@42" for
example) than a generic name ("pinctrl" or "stmfx-gpio")
to identify the device instance.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 12:01:53 +01:00
Patrick Delaunay
2c6df94c83 gpio: stm32: correct the bias management
Use the bias configuration for all the GPIO configurations and not
only for input GPIO, as indicated in Reference manual
(Table 81. Port bit configuration table).

Fixes: 43efbb6a3e ("gpio: stm32: add ops get_dir_flags")
Fixes: f13ff88b61 ("gpio: stm32: add ops set_dir_flags")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 12:01:46 +01:00
Patrick Delaunay
b305dbc08b pinctrl: stm32: display bias information for all pins
Display the bias information for input gpios or AF configuration,
and not only for output pin, as described in Reference manual
(Table 81. Port bit configuration table).

Fixes: da7a0bb1f2 ("pinctrl: stm32: add information on pin configuration")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 12:01:46 +01:00
Patrick Delaunay
9ed6f929a3 remoteproc: stm32: update error management in stm32_copro_start
The coprocessor is running as soon as the hold boot is de-asserted.

So indicate this running state and save the resource table even
if the protective assert, to avoid autonomous reboot, is failed.

This error case should never occurs.

Cc: Fabien DESSENNE <fabien.dessenne@st.com>
Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 11:32:31 +01:00
Patrick Delaunay
5a536dfe33 remoteproc: stm32: use reset for hold boot
Use the reset function to handle the hold boot bit in RCC
with device tree handle with MCU_HOLD_BOOT identifier.

This generic reset allows to remove the two specific properties:
- st,syscfg-holdboot
- st,syscfg-tz

This patch prepares alignment with kernel device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Fabien DESSENNE <fabien.dessenne@st.com>
Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 11:32:31 +01:00
Patrick Delaunay
d8d29a4489 reset: stm32: Add support of MCU HOLD BOOT
Handle the register RCC_MP_GCR without SET/CLR registers
but with a direct access to bit BOOT_MCU:
- deassert => set the bit: The MCU will not be in HOLD_BOOT
- assert => clear the bit: The MCU will be set in HOLD_BOOT

With this patch the RCC driver handles the MCU_HOLD_BOOT_R value
added in binding stm32mp1-resets.h

Cc: Fabien DESSENNE <fabien.dessenne@st.com>
Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 11:32:31 +01:00
Patrick Delaunay
29e5c02788 board: stm32mp1: no MTD partitions fixup for serial boot
Remove the update of the MTD partitions in kernel device tree
for serial boot (USB / UART), and the kernel will use the MTD
partitions define in the loaded DTB because U-Boot can't known the
expected flash layout in this case.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 10:58:15 +01:00
Richard Genoud
40426d6f9a SPL: stm32mp1: fix spl_mmc_boot_partition not defined
spl_mmc_boot_partition is only defined when
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is defined.

Signed-off-by: Richard Genoud <richard.genoud@posteo.net>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:56:09 +01:00
Marek Vasut
34d573fdab ARM: dts: stm32: Drop QSPI CS2 on DHCOM
The QSPI CS2 is not used on DHCOM, remove the pinmux and flash@1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:52:09 +01:00
Marek Vasut
64af7c3110 ARM: dts: stm32: Fix uSD card-detect GPIO on DHCOM
The uSD slot card-detect GPIO is connected to PG1, fix it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:50:44 +01:00
Marek Vasut
7d5164425b ARM: dts: stm32: Add DHCOM based PicoITX board
Add DT for DH PicoITX unit, which is a bare-bones carrier board for
the DHCOM. The board has ethernet port, USB, CAN, LEDs and a custom
board-to-board expansion connector.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:43:46 +01:00
Patrick Delaunay
77c077e171 arm: stm32mp: correct the ALIGN macro usage
Correct the ALIGN macro usage in mmu_set_region_dcache_behaviour
call: the address must use ALIGN_DOWN and size can use ALIGN macro.

With STM32_SYSRAM_BASE=0x2FFC0000 and MMU_SECTION_SIZE=0x100000 for
STM32MP15x the computed address was 30000000 instead of 2ff00000.

Fixes: 43fe9d2fda ("stm32mp1: mmu_set_region_dcache_behaviour")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:33:16 +01:00
Patrice Chotard
d5b0511391 ARM: dts: stm32: Fix typo in stm32h7-u-boot.dtsi
Fix typo "firsct"

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:29:23 +01:00
Patrice Chotard
183362947c ARM: dts: stm32: Fix timer initialization for stm32 MCU's board
Commit 4b2be78ab6 ("time: Fix get_ticks being non-monotonic")
puts in evidence that get_ticks is called before timer initialization.
Fix it by initializing timer before relocation.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:29:23 +01:00
Patrice Chotard
61c88ace4b ARM: dts: stm32: DT sync with kernel v5.10-rc1 for MCU's boards
Device tree alignment with kernel v5.10-rc1.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:29:23 +01:00
Patrice Chotard
63185b0a32 ARM: dts: sync armv7-m.dtsi with kernel v5.10-rc1
Since kernel v4.8-rc1, commit 05b23ebc2bd9 ("ARM: dts: armv7-m: remove skeleton.dtsi include"),
skeleton.dtsi file is no more included.

This synchronization is needed to avoid to get 2 memory node
in DTB file if, in DTS file, memory node is declared with the correct
syntax as following:

	memory@90000000 {
 		device_type = "memory";
 		reg = <0x90000000 0x800000>;
 	};

Then in DTB, we will have the 2 memory nodes, which is incorrect and
cause misbehavior during DT parsing by U-boot:

	memory {
		device_type = "memory";
		reg = <0x00 0x00>;
	};

	memory@90000000 {
		device_type = "memory";
		reg = <0x90000000 0x800000>;
	};

Issue found when synchronizing MCU's STM32 DT from kernel v5.10-rc1.
When using fdtdec_setup_mem_size_base() or fdtdec_setup_memory_banksize()
API, first above memory node is found (with reg = <0x00 0x00>), so
gd->ram_size, gd->ram_base, gd->bd->bi_dram[bank].start and
gd->bd->bi_dram[bank].size are all set to 0 which avoid boards to boot.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-25 10:29:23 +01:00
Tom Rini
d361eafe82 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- DWC2, DWC3 fixes
2020-11-22 11:00:11 -05:00
Tom Rini
6402887a9f Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- Assorted pinctrl updates
2020-11-22 10:59:49 -05:00
Jaehoon Chung
05dac23261 usb: gadget: dwc2_udc_otg: return zero when reset property is not present
If reset DT property is not present, -ENOENT is returned.
But it's not really error.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-11-22 13:18:20 +01:00
Siva Durga Prasad Paladugu
e7f9e1fca9 usb: dwc3: Handle case where setup_phy is not needed
If CONFIG_PHY is not enabled then the dwc3_setup_phy()
returns ENOTSUPP which can be still valid and intentional
so modify error check to handle this -ENOTSUPP.

The same error handling exists in drivers/usb/host/xhci-dwc3.c already
added by commit d648a50c0a ("dwc3: move phy operation to core.c").

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-11-22 13:18:20 +01:00
Patrick Delaunay
5739ef2bcb usb: dwc2: add "u-boot,force-vbus-detection" for stm32
On some board, the ID pin is not connected so the B session must be
overridden with "u-boot,force_b_session_valid" but the VBus sensing
must continue to be handle.

To managed it, this patch adds a new DT field
"u-boot,force-vbus-detection" to use with "u-boot,force_b_session_valid"

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-11-22 13:18:20 +01:00
Lad Prabhakar
46f3282b28 pinctrl: renesas: Drop unused members from struct sh_pfc_pinctrl
Drop unused members from struct sh_pfc_pinctrl.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-11-22 12:49:22 +01:00
Biju Das
2a589b7c51 pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A774E1
This driver supports both RZ/G2H and R-Car H3 SoCs.
Optimize pinctrl image size for RZ/G2H, when support for R-Car H3
(R8A7795) is not enabled

Based on the similar patch on Linux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-11-22 12:49:22 +01:00
Biju Das
8b00761c06 pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1
This driver supports both RZ/G2N and R-Car M3-N SoCs.
Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N
(R8A77965) is not enabled.

Based on the simialr patch on Linux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-11-22 12:49:22 +01:00
Biju Das
fee13ae8cb pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs.
Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+
(R8A7796[01]) is not enabled.

Based on the similar patch on Linux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-11-22 12:49:22 +01:00
Biju Das
975154bc2c pinctrl: renesas: r8a77951: Add R8A774E1 PFC support
Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (r8a77951),
however it doesn't have several automotive specific peripherals. Add
a r8a77951 specific pin groups/functions along with common pin
groups/functions for supporting both r8a77951 and r8a774e1 SoC.

PFC changes are synced from mainline linux-5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-11-22 12:49:22 +01:00
Biju Das
c5f3762588 pinctrl: renesas: r8a77965: Add R8A774B1 PFC support
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965),
however it doesn't have several automotive specific peripherals. Add
a r8a77965 specific pin groups/functions along with common pin
groups/functions for supporting both r8a77965 and r8a774b1 SoC.

PFC changes are synced from mainline linux-5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-11-22 12:49:22 +01:00
Tom Rini
12e396303c Pull request for UEFI sub-system for efi-2021-01-rc3 (2)
The parameter check for UEFI service GetNextVariableName() is corrected.
 
 The dependencies of CONFIG_DFU_TFTP are simplified.
 
 The set of supported hash algorithms reported by the EFI_TCG2_PROTOCOL is
 corrected.
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Merge tag 'efi-2021-01-rc3-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2021-01-rc3 (2)

The parameter check for UEFI service GetNextVariableName() is corrected.

The dependencies of CONFIG_DFU_TFTP are simplified.

The set of supported hash algorithms reported by the EFI_TCG2_PROTOCOL is
corrected.
2020-11-21 08:04:39 -05:00
Heinrich Schuchardt
7e5875a856 efi_loader: parameter check in GetNextVariableName()
If GetNextVariableName() is called with a non-existing combination of
VariableName and VendorGuid, return EFI_INVALID_PARAMETER.

If GetNextVariableName() is called with a string that is not zero
terminated, return EFI_INVALID_PARAMETER.

Reformat a line over 80 characters.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-11-21 07:26:16 +01:00
Ilias Apalodimas
9aeb380277 efi_loader: tcg2 protocol updates
On pull reuqest
https://lists.denx.de/pipermail/u-boot/2020-November/432735.html
V4 of the patchset was sent instead of the v5.
This is the v4->v5 missing diff

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2020-11-21 07:26:16 +01:00