Commit graph

24864 commits

Author SHA1 Message Date
Harini Katakam
414fc91f4e arm64: zynqmp: Increase reset assert time for TI SGMII PHY
Increase reset assert time for TI SGMII PHY on KR260 CC starting
6.1 kernel. This PHY does not come out of reset with the existing
100us pulse width as per testing on multiple carrier cards. The reset
is driven via a PCA9570 I2C expander. The expander driver was updated
to an upstream version in 6.1 where gpio_chip _set was optimized.
Delays in earlier kernels may have masked this issue. This is a safe
workaround value for assert pulse width before the discussions are
resolved with TI.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Michal Simek
369d04d643 arm64: zynqmp: Fix gpio comment about No of gpios
There are total 174 gpios but from 0 - 173 that's why fix comment to
reflect it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c7e94b334e7dd6297e0d3a36a6a3d04bd7e9e967.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Harini Katakam
f668961485 arm64: zynqmp: Assign TSU clock frequency for KR260
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KR260 CC to allow PTP functionality.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Parth Gajjar
d95fc99a74 arm64: zynqmp: Update MALI 400 interrupt and clock names
Motivation for the commit is to utilize the upstream community
device tree so that the either modified ARM Mali 400 driver
or upstream lima driver can be used.

Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Manikanta Guntupalli
28dc356e66 xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by
Linux.
"enforced open drain please flag it properly in DT/ACPI DSDT/board
file."

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Varalaxmi Bingi
39bdb96498 arm: xilinx: Setting default i2c clock frequency to 400kHz
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of
400kHz. Current default value is 100kHz.

Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Michal Simek
174d728471 arm64: zynqmp: Switch to amd.com emails
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Michal Simek
5b90412cbf xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h
zynqmp_mmio_read/write() are firmware provided hooks that's why use only
zynqmp_firmware.h for function declaration.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
37688da586 xilinx: versal-net: Add mini eMMC 5.1 configuration
Add support for Versal NET mini eMMC 5.1 configuration. Add device tree
and defconfig.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
38e0fc06b2 xilinx: versal-net: Add mini ospi configuration
Add support for Versal NET mini Octal SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Octal SPI
related settings are enabled.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
96683d3436 xilinx: versal-net: Add mini qspi configuration
Add support for Versal NET mini Quad SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Quad SPI
related settings are enabled.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
34dec6a443 cadence_qspi: Enable flash reset for Versal NET platform
Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.

Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.

Add read_delay initialization for Versal NET also.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Sharath Kumar Dasari
85a2d124cd arm64: zynqmp: Fix the memory node for k26/k24 kria som boards
PMUFW requires top 1MB of the lower DDR memory reserved for its operation,
this is missing in k26/k24 sm static dts files because of which U-Boot
throws warning messages "efi_free_pool: illegal free" as EFI puts
some code to that space which shouldn't happen.

Signed-off-by: Sharath Kumar Dasari <sharath.kumar.dasari@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/57452d16df2d48593de206bebf877d2c2cfe7bf1.1685966389.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Tom Rini
e896279ac3 binman mkimage and template enhancements
misc fixes
 -----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAmS5lQQRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIreYiowgAzKVER9eU9rWDCP76GXpxwBmNUDYeS/hQ
 ivzmzcvs7luo78LpSbVHGzTNM4cQ/KUViCl4nxvBlLlKLoOTKFf9R0wv7AnBM16X
 cNARdffqfTdoptBBoJnhuHPpvVQ9M22YcTQSMaD9FvlCmAHdBaiP4T4wN04Ulckb
 u7zeQYiy/nQfFP4KxsPw3looHGNz3LaKgXw3fvbBVOsGcVR5avASLpxoEOwNbWA4
 +NcvpAqdkJ1CRjJRrVPjGqNudef69E4xjPzmoRd9Ni2HXJsSD3FoEelfKbhgovpD
 Ss23tUycbQrJyFnQj1lYiKeZRtEGBKxQUvZqhdaDg6cileRXP803HA==
 =o9IH
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-20jul23' of https://source.denx.de/u-boot/custodians/u-boot-dm

binman mkimage and template enhancements
misc fixes
2023-07-20 21:31:31 -04:00
Mikhail Kalashnikov
ecb896cec7 sunxi: H616: add LPDDR3 DRAM support
The H616 SoC has support for several types of DRAM: DDR3, LPDDR3,
DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 memory.
Let's extend the driver to support the LPDDR3 memory. All "magic"
values obtained from the boot0.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21 00:54:19 +01:00
Mikhail Kalashnikov
5d6f013adc sunxi: H616: add DRAM type selection
Allwinner H616 SoC supports several types of DRAM memory. To further
integrate other types of memory, we need to add this delimitation.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21 00:54:13 +01:00
Andre Przywara
78aa00c38e sunxi: H616: dram: split struct dram_para
Currently there is one DRAM parameter struct for the Allwinner H616 DRAM
"driver". It contains many fields that are compile time constants
(set by Kconfig variables), though there are also some fields that are
probed and changed over the runtime of the DRAM initialisation.

Because of this mixture, the compiler cannot properly optimise the code
for size, as it does not consider constant propagation in its full
potential.

Help the compiler out by splitting that structure into two: one that only
contains values known at compile time, and another one where the values
will actually change. The former can then be declared "const", which will
let the compiler fold its values directly into the code using it.

We also add "const" tags for some new "struct dram_config" pointers, to
further increase code optimisation.
To help the compiler optimise the code further, the definition of the
now "const struct dram_para" has to happen at a file-global level, so
move that part out of sunxi_dram_init().

That results in quite some code savings (almost 2KB), and helps to keep
the code small with the LPDDR3 support added later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:29:42 +01:00
Andre Przywara
457e2cd665 sunxi: H616: dram: const-ify DRAM function parameters
There are quite some functions in the Allwinner H616 DRAM "driver", some
of them actually change the parameters in the structure passed to them,
but many are actually not.
To increase the optimisation potential for the code, mark those functions
that just read members of the passed dram_para struct as "const".
This in itself does not decrease the code size, but lays the groundwork
for future changes doing so.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:29:42 +01:00
Andre Przywara
c9dd624a38 sunxi: dram: make MBUS configuration functions static
The usage of the C keyword "inline" seems to be a common
misunderstanding: it's a *hint* only, and modern compilers will inline
(or not) functions based on their own judgement and provided compiler
options.
So while marking functions as "inline" does not do much, missing the
"static" keyword will force to compiler to spell out a version of the
function for potential external callers, which actually increases the
code size (though hopefully the linker will drop the function).

Change the "inline" attribute for the mbus_configure_port() functions in
some Allwinner DRAM drivers to "static", so that the explicit version
can actually be dropped from the object file, reducing the code size.

"static inline" has a use case in header files, where it avoids a warning
if a .c file including this header does not use the particular function.
In a .c file itself "static inline" is not useful otherwise, so just use
static here as well.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:29:42 +01:00
Andre Przywara
fcd9220d66 sunxi: Kconfig: rework PHY_USB_SUN4I selection
At the moment we use "select" in each Allwinner SoC's Kconfig section to
include the USB PHY driver in the build. This means it cannot be disabled
via Kconfig, although USB is not really a strictly required core
functionality, and a particular board might not even include USB ports.

Rework the Kconfig part by removing the "select" lines for each SoC's
section, and instead letting it default to "y" in the PHY driver section
itself. We use "depends on !" to exclude the few SoCs we don't support
(yet). The Allwinner V3s does not enable USB (PHY) support at the moment,
even though it should work: let the PHY default to "n" to keep the
current behaviour.

Also the MUSB USB driver directly calls some functions from the PHY
driver, so let the former depend on the PHY driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
2023-07-21 00:26:36 +01:00
Simon Glass
8163907adf stm32mp15: Avoid writing symbols in SPL
These boards use SPL in a mkimage entry and apparently access the symbol
containing the image position of U-Boot, but put U-Boot in another
image. This means that binman is unable to fill in the symbol correctly
in the SPL binary.

This doesn't matter at present since mkimage doesn't support symbol
writing. But with the upcoming conversion to a section, it will. So add
a property to disable symbol writing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-20 14:10:58 -06:00
Sergei Antonov
76e1607617 sandbox: fix a compilation error
With sandbox and sandbox64 configurations:

In file included from .../u-boot/include/test/test.h:156,
                 from .../u-boot/include/test/lib.h:9,
                 from .../u-boot/test/lib/test_crc8.c:8:
.../u-boot/arch/sandbox/include/asm/test.h: In function ‘sandbox_sdl_set_bpp’:
.../u-boot/arch/sandbox/include/asm/test.h:323:17: error: ‘ENOSYS’ undeclared (first use in this function)
  323 |         return -ENOSYS;
      |                 ^~~~~~

Per Tom Rini's suggestion:
move that function prototype over to arch/sandbox/include/asm/sdl.h
and make test/dm/video.c include <asm/sdl.h>

Cc: Simon Glass <sjg@chromium.org>
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-20 14:10:57 -06:00
Tom Rini
9ef4166ff9 arm: mx5: Correct mxc_set_clock function prototype
With gcc-13.1 we get a warning about enum vs int here, so correct the
declaration to match the implementation.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-20 14:48:20 -04:00
Tom Rini
bfbab7b27e mips: octeon: Correct types in cvmx-pko3-queue
When building with gcc-13.1 we see that the prototype for
cvmx_pko3_sq_config_children does not match the declaration. Make these
match and correct a typo in the function's version of the docs that the
prototype did not have, as part of keeping those in-sync.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-20 14:48:20 -04:00
Tom Rini
5dcfc99b2b Merge tag 'fsl-qoriq-2023-7-13' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Enable DM_SERIAL for T2080RDB, T4240RDB, T1042D4RDB, T1024RDB
2023-07-19 07:59:34 -04:00
Simon Glass
b8956425d5 x86: Switch QEMU over to use the bochs driver
This is more convenient since it does not require a video BIOS. Enable
it for QEMU.

Also drop use of video in SPL for the 64-bit QEMU, since it not needed
now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:15 +08:00
Simon Glass
dac1fa5c19 x86: Make sure that the LPC is active before SDRAM init
Some boards need to access GPIOs to determine which SDRAM is fitted to the
board, for example chromebook_link. Probe this device (if it exists) to
make sure that this works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:15 +08:00
Simon Glass
df1bb2cb0b x86: link: Support Micron memory
Add the required tag so that micron memory can be set up correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:15 +08:00
Simon Glass
e2e7de8747 x86: Convert some debug statements to use logging
Move from using debug() to log_debug() so that we don't have to use the
__func__ parameter and can access other logging features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:14 +08:00
Simon Glass
6a32489782 x86: Record the start and end of the tables
The ACPI tables are special in that they are passed to EFI as a separate
piece, independent of other tables.

Also they can be spread over two areas of memory, e.g. with QEMU we end
up with tables kept in high memory as well.

Add new global_data fields to hold this information and update the bdinfo
command to show the table areas.

Move the rom_table_end variable into the loop that uses it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:08 +08:00
Simon Glass
8856d613cb x86: Refactor table-writing code a little
The implementation of write_tables() is confusing because it uses the
rom_table_start variable as the address pointer as it progresses.

Rename it to rom_addr to make the code clearer. Move the rom_table_end
variable into the block where it is used.

Also update logging to use the ACPI category, now that it is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
e7595aa350 x86: Allow logging to be used in SPL reliably
When global_data is relocated, log_head moves in memory, meaning that
the items in that list point to the wrong place.

Disable logging when making the change, then reenable it afterwards, so
that logging works normally.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
7c10e111c1 x86: Init video in SPL if enabled
When video is required in SPL, set this up ready for use. Ignore any
problems since it may be that video is not actually available and we
still want to continue on to U-Boot proper in that case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
3525258019 x86: Ensure SPL banner is only shown once
Print the banner in SPL init only if the spl_board_init() function isn't
enabled. The spl_board_init() function is in the same file, but is called
later, by board_init_r().

This avoids printing two banners, which causes tests to fail.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
5345700d2a x86: Allow video-BIOS code to be built for SPL
With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e.
SPL. Add a Kconfig option for this, adjust the Makefile rules and use
CONFIG_IS_ENABLED() where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
8f015d3781 x86: Improve the trampoline in 64-bit mode
At present this leaves the stack at the pre-relocation value. This is not
ideal since we want to have U-Boot running entirely from the top of
memory.

In addition, the new global_data pointer is not actually used, since
the global_data pointer itself is relocated, then the pre-relocation value
is changed, so the effective value (after relocation) does not update.

Adjust the implementation to follow the 32-bit code more closely, with a
trampoline function which is passed the new stack and global_data pointer.
This ensures that the correct values come through even when relocating.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:07 +08:00
Simon Glass
78f24d8f34 x86: Show an error when a BIOS exception occurs
Rather than silently hanging, show an error first. This can happen when
there is something wrong with the video BIOS.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
67884002f4 x86: Correct get_sp() implementation for 64-bit
Use an assembler implementation as is done for i386, so that the results
are equivalent for i386 and x86_64.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
633af11dd6 x86: Show the CPU physical address size with bdinfo
This is useful information so show it with the bdinfo command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
de94db8132 x86: Add a comment for board_init_f_r_trampoline()
Add a comment for this function in the header.

Change the function (and the one after) to use __noreturn to keep
checkpatch happy.

Add docs to board_init_f_r() while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
b73dba7a83 x86: Tidy up EFI code in interrupt_init()
The ll_boot_init() check handles the EFI case so we don't need the rest
of the code. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
4fb2536e5b x86: Allow listing MTRRs in SPL
Move MTRR-listing code into a common file so it can be used from SPL.
Update the 'mtrr' command to call it.

Use this in SPL just before adjusting the MTRRs, so we can see the state
set up by the board. Only show it when debug is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
d0dfbf548d x86: zimage: Export the function to obtain the cmdline
Allow reading the command line from a zimage, so that it can be recorded
in the bootflow.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-17 13:38:35 +08:00
Simon Glass
c886557c18 x86: Add a function to boot a zimage
Add a direct interface to booting a zimage, so that bootstd can call it
without going through the command-line interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 13:38:35 +08:00
Christophe Leroy
64948e247e powerpc: Fix flush_cache() speed regression
Flushing kernel image after decompression was taking 113 milliseconds
with U-boot 2022.10. With U-boot 2023.01 and 2023.04, flushing
the same amount of memory takes approx 1.5 seconds. With
U-boot 2023.07-rc6, it takes 6.5 seconds.

powerpc flush_cache() function used to call WATCHDOG_RESET() after
flushing every cacheline. At that time WATCHDOG_RESET() was light
so the operation was almost seamless.

But commit 29caf9305b ("cyclic: Use schedule() instead of
WATCHDOG_RESET()") replaced WATCHDOG_RESET() by schedule() and that
started to hurt with U-boot 2022.10.

And in U-boot 2023.07-rc6 that's even worse after
commit 26e8ebcd7c ("watchdog: mpc8xxx: Make it generic").

In the meantime commit 729c1fe656 ("powerpc: introduce
CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD") gives us the opportinity to
only call schedule() every given chunk of data instead of every
cacheline. As explained in that commit there is no point in pinging
the watchdog after every cacheline flush, so lets define a sensible
default chunk size of 4k which matches to size of a page on most
powerpc platforms.

With that new default threshold, the culprit flushing performed after
kernel image decompression now takes 85 milliseconds on a powerpc 8xx.

Fixes: 29caf9305b ("cyclic: Use schedule() instead of WATCHDOG_RESET()")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-07-14 15:21:08 -04:00
Jim Liu
d136610988 arch: arm: npcm8xx: add cpu version and 4G ram support
Add npcm8xx A2 cpu version check
and add 4G RAM support

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14 15:21:07 -04:00
Jim Liu
7870043c4b ARM: dts: npcm8xx: fix dts node error
The SHA and OTP should under the ahb node

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14 15:21:07 -04:00
Simon Glass
87c1a4130c expo: Add tests for the configuration editor
Add some simple tests and a helpful script to make the configuration
editor easier to set up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14 12:54:51 -04:00
Simon Glass
82cafee133 expo: Support building an expo from a description file
The only way to create an expo at present is by calling the functions to
create each object. It is useful to have more data-driven approach, where
the objects can be specified in a suitable file format and created from
that. This makes testing easier as well.

Add support for describing an expo in a devicetree node. This allows more
complex tests to be set up, as well as providing an easier format for
users. It also provides a better basis for the upcoming configuration
editor.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14 12:54:51 -04:00
Simon Glass
7230fdb383 expo: Add spacing around menus and items
It looks better if menus have a bit of an inset, rather than be drawn hard
up against the background. Also, menu items look better if they have a bit
of spacing between them.

Add theme options for these and implement the required changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14 12:54:51 -04:00