Commit graph

307 commits

Author SHA1 Message Date
Wills Wang
ca09e66b04 mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define
Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-31 10:17:54 +02:00
Wills Wang
cdeb68e292 mips: ath79: Add support for ungating USB and ethernet on qca953x
Add code to ungate USB and ethernet controller on qca953x

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-31 10:17:54 +02:00
Wills Wang
04583c686e mips: ath79: ap121: Enable ethernet
This patch enable network function for ap121 board.

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-05-31 10:17:54 +02:00
Wills Wang
375239174c mips: ath79: Rename get_bootstrap into ath79_get_bootstrap
Add a platform prefix for function name in order to make more readable,
and move it into ath79.h

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-05-31 10:17:54 +02:00
Paul Burton
fb64cda579 MIPS: Abstract cache op loops with a macro
The various cache maintenance routines perform a number of loops over
cache lines. Rather than duplicate the code for performing such loops,
abstract it out into a new cache_loop macro which performs an arbitrary
number of cache ops on a range of addresses. This reduces duplication in
the existing L1 cache maintenance code & will allow for not adding
further duplication when introducing L2 cache support.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31 09:44:24 +02:00
Paul Burton
372286217f MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:44:24 +02:00
Paul Burton
ace3be4f15 MIPS: Move cache sizes to Kconfig
Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31 09:44:24 +02:00
Daniel Schwierzeck
83b0face8c MIPS: remove dead code from asm/u-boot-mips.h
Those wrappers for linker symbols were once used in the MIPS
specific board.c implementation. Since the migration to generic
board.c, those wrappers are dead code and can be removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:38:11 +02:00
Daniel Schwierzeck
5f9cc363ed MIPS: add tune for MIPS 34kc
Add tune Kconfig option for MIPS 34kc.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:38:11 +02:00
Daniel Schwierzeck
07f5b966aa MIPS: provide a default u-boot-spl.lds
Provide a default linker script for SPL binaries. Start address
and size of text section and BSS section are configurable. All
sections are arranged in a way that only relevant sections are
kept in the code section for maximum size reduction. All other
sections are kept but moved outside the code section to help
with debugging.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-05-31 09:38:11 +02:00
Paul Burton
0f832b9cdc malta: Allow MIPS64 builds
Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31 09:38:11 +02:00
Paul Burton
2e4cc1c5d4 MIPS: Use CPHYSADDR to implement mips32 virt_to_phys
Use CPHYSADDR to implement the virt_to_phys function for converting from
a virtual to a physical address for MIPS32, much as is already done for
MIPS64. This allows for virt_to_phys to work regardless of whether the
address being translated is in kseg0 or kseg1, unlike the previous
subtraction based approach which only worked for addresses in kseg0.
This allows for drivers to provide an address to virt_to_phys without
needing to manually ensure that kseg1 addresses are converted to
equivalent kseg0 addresses first.

This patch is equivalent to this Linux patch currently waiting to be
reviewed & merged:

    https://patchwork.linux-mips.org/patch/12564/

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31 09:38:11 +02:00
Simon Glass
3e085c9946 mips: Drop unused code in u-boot.h
Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-27 15:39:53 -04:00
Wills Wang
4349b55b99 mips: ath79: ar933x: Avoid warning with gcc5
GCC 5.3 report a warning: 'upper' and 'lower' may be used
uninitialized in this function [-Wmaybe-uninitialized].
Compiler might need explicit initializer.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-26 01:34:14 +02:00
Wills Wang
42a3f3e6eb mips: ath79: ar933x: Fix ethernet PHY mismatch
We need reset the Ethernet Switch analog part before operation,
or the build-in Ethernet PHY don't work.

Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
2016-05-26 01:34:14 +02:00
Marek Vasut
1ad3a6fb5b mips: Drop JZ4740 remnants
Remove the remnants of JZ4740 support.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2016-05-26 01:34:14 +02:00
Marek Vasut
ecc9d26062 mips: Allow overriding start.S in SPL
Certain chips, like the JZ47xx, have extreme size constraints on the
SPL size and require custom start.S . Allow overriding the start.S
the same way ARM MXS does it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2016-05-26 01:34:14 +02:00
Paul Burton
6242aa1374 malta: Use device model & tree for UART
Make use of device model & device tree to probe the UART driver. This is
the initial step in bringing Malta up to date with driver model, and
allows for cleaner handling of the different I/O addresses for different
system controllers by specifying the ISA bus address instead of a
translated memory address.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-26 01:34:13 +02:00
Paul Burton
40ba13c986 malta: Support MIPS32r6 configurations
Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6
CPUs. Allow building U-Boot for such systems by selecting
CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-21 01:36:39 +02:00
Paul Burton
c52ebea1cc MIPS: Support for targetting MIPSr6
Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way
that we currently select release 1 or release 2 targets. MIPSr6 is not
entirely backwards compatible with earlier releases of the architecture.
Some instructions are encoded differently, some are removed, some are
reused, so it is not practical to run U-Boot built for earlier revisions
on a MIPSr6 system. Update their Kconfig help text to reflect that.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-21 01:36:39 +02:00
Paul Burton
20286cdff7 MIPS: Simplify CONFIG_SYS_CPU values
Rather than having the values for CONFIG_SYS_CPU depend upon each
architecture revision, have them depend upon the more general
CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the
architecture revisions.

This is done in preparation for adding MIPSr6 support, which would
otherwise need to introduce new cases here.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-21 01:36:39 +02:00
Paul Burton
9f8ac82452 MIPS: Use unchecked immediate addition/subtraction
In MIPS assembly there have historically been 2 variants of immediate
addition - the standard "addi" which traps if an overflow occurs, and
the unchecked "addiu" which does not trap on overflow. In release 6 of
the MIPS architecture the trapping variants of immediate addition &
subtraction have been removed. In preparation for supporting MIPSr6,
stop using the trapping instructions from assembly & switch to their
unchecked variants.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-21 01:36:39 +02:00
Marek Vasut
400df30998 mips: ath79: Add support for TPLink WDR4300
Add support for the TPLink WDR4300 router, which is based on the
AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported
on this system as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:39 +02:00
Marek Vasut
e08539b791 mips: ath79: Add AR934x support
Add support for the Atheros AR934x WiSoCs. This patchs adds complete
system init, including PLL and DRAM init, both of which happen from
full C environment, since the AR934x has proper SRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:39 +02:00
Marek Vasut
4771bbee5d mips: ath79: Add support for ungating ethernet on ar933x and ar934x
Add code to ungate the ethernet controller on ar933x and ar934x .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
2986a9d4bd mips: ath79: dts: Add ethernet MAC nodes for ar933x
Add node for both ethernet controllers in the ar933x.
The PHY is attached only to the first ethernet controller.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
6b699742d4 mips: ath79: Add support for ungating USB on ar933x and ar934x
Add code to ungate the USB controller on ar933x and ar934x .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
c31558780b mips: ath79: dts: Add generic-ehci node
Add generic EHCI node for the ChipIdea EHCI controller in the ath79.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
43a092ffdd mips: ath79: Fix compiler warning on const assignment
The assignment const T var; var = value; is illegal, since var is
constant. Drop the const to fix the compiler warning.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
0a6767efab mips: ath79: Fix ar71xx_regs.h indent
The indent in this file triggers my OCD, so fix it. Replace multiple
spaces with tabs and align the values in one column.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
0a0a958b68 mips: Add MIPS 74Kc tune
Add MIPS 74Kc tune Kconfig option.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
[added missing tune-y entry in arch/mips/Makefile]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:36:38 +02:00
Marek Vasut
5760fc7850 mips: Fix compiler warning in cpu.c
There really is zero reason for including netdev.h in generic mips CPU code.
Removing the netdev.h from cpu.c also fixes the following compiler warning:

In file included from arch/mips/cpu/cpu.c:10:0:
include/netdev.h:204:41: warning: 'struct eth_device' declared inside parameter list [enabled by default]
 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
                                         ^
include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:36:38 +02:00
Wills Wang
59e4080c7e ath79: add readonly attribute for ath79_soc_desc
use 'const' keywork to qualify readonly attribute for lookup-table member

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Wills Wang
5691d10a01 ath79: ar933x: use BIT macro for bit shift operation
used a uniform BIT macro for register bit-field shift

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:36:38 +02:00
Wills Wang
a2277cc30c mips: ath79: add AP143 reference board
This patch add board-level code and base DT for AP143.

Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:25:50 +02:00
Wills Wang
6a7b52bc8d mips: ath79: add AP121 reference board
This patch add board-level code and base DT for AP121.

Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-21 01:25:50 +02:00
Wills Wang
9b03f802ae mips: ath79: add support for QCA953x SOCs
This patch enable work for qca953x SOC.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:25:50 +02:00
Wills Wang
ee7bb5be35 mips: ath79: add support for AR933x SOCs
This patch enable work for ar933x SOC.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:25:50 +02:00
Wills Wang
1d3d0f1f1c mips: add base support for QCA/Atheros ath79 SOCs
This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:25:50 +02:00
Robert P. J. Day
1cc0a9f496 Fix various typos, scattered over the code.
Spelling corrections for (among other things):

* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
2016-05-05 21:39:26 -04:00
Purna Chandra Mandal
fdff5b0598 MIPS: bootm: Add fixup of '/memory' node.
MIPS arch do not update 'reg' property of /memory node.
As a result Linux bootup will not work unless board.dts
file contains right /memory offset-size information or
board implements required memory fixup.
Fixing by renaming (unused) _arch_fixup_memory_node_ to
_arch_fixup_fdt_ in arch/mips/lib/bootm.c inline with ARM arch.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-04-19 13:21:48 +02:00
Purna Chandra Mandal
ac7eef716e board: pic32mzda: enable USB-host, USB-storage support.
Enable MUSB host and USB storage support for Microchip
PIC32MZ[DA] Starter Kit.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-04-10 17:18:42 +02:00
Matthias Schiffer
499b847521 MIPS: fix mips_cache fallback without __builtin_mips_cache
The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register
instead.

Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-03-09 11:00:40 +01:00
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Purna Chandra Mandal
7d514a7407 board: Enable ethernet, tftpboot support to pic32mzdask board.
This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-02-01 22:14:02 +01:00
Purna Chandra Mandal
c76eb72c43 board: add SDHCI support for PIC32MZDASK board.
Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
2016-02-01 22:14:02 +01:00
Purna Chandra Mandal
44da3a176c board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
be961fa15b MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
Add Microchip PIC32MZ[DA] SoC family support.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
9ffa7a35ef drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01 22:14:01 +01:00
Purna Chandra Mandal
32c1a6eef8 MIPS: initial infrastructure for Microchip PIC32 architecture
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-02-01 22:14:00 +01:00