Commit graph

39 commits

Author SHA1 Message Date
Poonam Aggrwal
0e870980a6 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx
The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Poonam Aggrwal
18bacc2027 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Peter Tyser
017f11f68e 8xxx: Break out DMA code to a common file
DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
previous CONFIG_DDR_ECC

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01 23:01:51 -05:00
Kumar Gala
480f617905 86xx: Add CPU_TYPE_ENTRY support
Unify with 83xx and 85xx and use CPU_TYPE_ENTRY.  We are going to use
this to convey the # of cores and DDR width in the near future so its
good to keep in sync.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-30 08:24:22 -05:00
Peter Tyser
2f21ce4d54 fsl/85xx, 86xx: Sync up DMA code
The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:

85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register.  These bits
  only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
  status register.  We may as well clear all 32 bits of the register...

86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
  the controller
- Clear the channel start bit in the DMA mode register after a transfer

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:17:58 -05:00
Peter Tyser
b1f12650d3 fsl: Create common fsl_dma.h for 85xx and 86xx cpus
Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:17:45 -05:00
Peter Tyser
f9a109b3ad Replace __attribute references with __attribute__
__attribute__ follows gcc's documented syntax and is generally more
common than __attribute.  This change is only asthetic and should not
affect functionality.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-04-28 01:01:39 +02:00
Peter Tyser
a1c8a71926 86xx: Update CPU info output on bootup
- Update style of 86xx CPU information on boot to more closely
  match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output

== Before ==
Freescale PowerPC
CPU:
    Core: E600 Core 0, Version: 0.2, (0x80040202)
    System: Unknown, Version: 2.1, (0x80900121)
    Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
    L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC

== After ==
CPU:   8641D, Version: 2.1, (0x80900121)
Core:  E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
       CPU:1066.667 MHz, MPX:533.333 MHz
       DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1:    D-cache 32 KB enabled
       I-cache 32 KB enabled
L2:    512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-16 18:05:57 -06:00
Peter Tyser
4ef630df77 86xx: Reset update
Update the 86xx reset sequence to try executing a board-specific reset
function.  If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ.  Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-16 18:05:56 -06:00
Wolfgang Denk
a9f3acbcd0 MPC86xx: fix build warnings
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-12 14:50:35 +01:00
Trent Piepho
ada591d2a0 mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.

This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.

The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.

get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.

checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:49 -06:00
Trent Piepho
9863d6aca1 mpc86xx: Double local bus clock divider
The local bus clock divider should be doubled for both 8610 and 8641.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:48 -06:00
Trent Piepho
a5d212a263 mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:20:25 -06:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Andy Fleming
75b9d4ae0d Pass in tsec_info struct through tsec_initialize
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:15 -07:00
Jon Loeliger
859f24350e Merge commit 'wd/master' 2008-07-10 12:05:32 -05:00
Wolfgang Denk
4188f04918 Minor coding style cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-07-10 01:13:30 +02:00
Jason Jin
3473ab7372 Feed the watchdog in u-boot for 8610 board.
The watchdog on 8610 board is enabled by setting sw[6]
to on. Once enabled, the watchdog can not be disabled
by software. So feed the dog in u-boot is necessary for
normal operation.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-07-07 11:29:48 -05:00
Ben Warren
dd35479a50 Add mechanisms for CPU and board-specific Ethernet initialization
This patch is the first step in cleaning up net/eth.c, by moving Ethernet
initialization to CPU or board-specific code.  Initial implementation is
only on the Freescale TSEC controller, but others will be added soon.

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-07-06 00:20:59 -07:00
Becky Bruce
e34a0e911b PPC: 86xx Add bat registers to reginfo command
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-03 18:05:15 +02:00
Andy Fleming
1ced121600 Update SVR numbers to expand support
FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26 11:43:04 -05:00
Jon Loeliger
13f5433f70 86xx: Convert sbc8641d to use libfdt.
This is the proper fix for a missing closing brace in the function
ft_cpu_setup() noticed by joe.hamman <at> embeddedspecialties.com.
The ft_cpu_setup() function in mpc8641hpcn.c should have been
removed earlier as it was under the obsolete CONFIG_OF_FLAT_TREE,
but was missed.  Only, the sbc8641d was nominally still using it.
It all got ripped out, and the funcality that was in ft_board_setup()
was refactored to remove the CPU portions into the new file
cpu/mpc86xx/fdt.c instead.  Make sbc8641d use this now.

Based loosely on an original patch from joe.hamman@embeddedspecialties.com

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-02-18 14:01:56 -06:00
Becky Bruce
4f93f8b1a4 86xx: Add reginfo command
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-01-24 12:12:56 -06:00
Jason Jin
a8318ec205 make 8610 board use pixis reset
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2007-11-07 14:08:45 -06:00
Jon Loeliger
9553df86d3 Initial mpc8610hpcd cpu/, README and include/ files.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-10-17 15:01:47 -05:00
Kim Phillips
255a3577c8 Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx
For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-05-17 00:07:21 +02:00
Jon Loeliger
bd7851ce1e mpc86xx; Write MAC address to mac-address and local-mac-address
Some device trees have a mac-address property, some have local-mac-address,
and some have both.  To support all of these device trees, ftp_cpu_setup()
should write the MAC address to mac-address and local-mac-address, if they
exist.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-04-20 14:12:26 -05:00
Jon Loeliger
7dbdf28b8b mpc86xx: protect memcpy to bad address if a mac-address is missing from dt
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-04-20 14:11:38 -05:00
Haiying Wang
3d98b85800 Add PIXIS FPGA support for MPC8641HPCN board.
Move the 8641HPCN's PIXIS code to the new directory
board/freescale/common/ as it will be shared by
future boards not in the same processor family.

Write a "pixis_reset" command that utilizes the FPGA
reset sequencer to support alternate soft-reset options
such as using the "alternate" flash bank, enabling
the watch dog, or choosing different CPU frequencies.

Add documentation for the pixis_reset to README.mpc8641hpcn.

Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-04-09 14:25:05 -05:00
Jon Loeliger
d14ba6a798 Handle 86xx SVR values according to the new Reference Manual.
Both 8641 and 8641D have SVR == 0x8090, and are distinguished
by the byte in bits 16-23 instead.
Thanks to Jason Jin for noticing.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-09-14 08:40:36 -05:00
Jon Loeliger
ffff3ae56f General indent and whitespace cleanups. 2006-08-22 12:06:18 -05:00
Jon Loeliger
709d3073e7 Convert to mac-address in ethernet nodes. 2006-08-09 09:00:30 -05:00
Jon Loeliger
cb5965fb95 White space cleanup.
Some 80-column cleanups.
Convert printf() to puts() where possible.
Use #include "spd_sdram.h" as needed.
Enhanced reset command usage message a bit.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-05-31 12:44:44 -05:00
Jon Loeliger
4d3d729c16 Moved mpc8641hpcn_board_reset() out of cpu/ into board/.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-05-31 11:24:28 -05:00
Jon Loeliger
b2a941de06 Remove dead debug code.
Signed-off-by: Jon Loeliger <jdl@jdl.com>
2006-05-31 10:07:28 -05:00
Jon Loeliger
126aa70f10 Move mpc86xx PIXIS code to board directory
First cut at moving the PIXIS platform code out of
the 86xx cpu directory and into board/mpc8641hpcn
where it belongs.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2006-05-31 09:49:33 -05:00
Haiying Wang
38cee12dcf Improve "reset" command's interaction with watchdog.
"reset altbank" will reset another bank WITHOUT watch dog timer enabled
    "reset altbank wd" will reset another bank WITH watch dog enabled
    "diswd" will disable watch dog after u-boot boots up successfully

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2006-05-30 09:10:32 -05:00
Jon Loeliger
5c9efb36a6 Cleanup whitespaces and style issues.
Removed //-style comments.
Use 80-column lines.
Remove trailing whitespace.
Remove dead code and debug cruft.
2006-04-27 10:15:16 -05:00
Jon Loeliger
debb7354d1 Initial support for MPC8641 HPCN board. 2006-04-26 17:58:56 -05:00