mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-18 06:58:54 +00:00
White space cleanup.
Some 80-column cleanups. Convert printf() to puts() where possible. Use #include "spd_sdram.h" as needed. Enhanced reset command usage message a bit. Signed-off-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Jon Loeliger
parent
3d5c5be547
commit
cb5965fb95
2 changed files with 127 additions and 121 deletions
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@ -38,12 +38,13 @@ extern void ft_cpu_setup(void *blob, bd_t *bd);
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#include "pixis.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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extern long int spd_sdram(void);
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#if defined(CONFIG_SPD_EEPROM)
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#include "spd_sdram.h"
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#endif
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void sdram_init(void);
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long int fixed_sdram(void);
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@ -51,7 +52,7 @@ long int fixed_sdram(void);
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int board_early_init_f (void)
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{
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return 0;
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return 0;
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}
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int checkboard (void)
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@ -60,34 +61,32 @@ int checkboard (void)
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#ifdef CONFIG_PCI
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile ccsr_pex_t *pex1 = &immap->im_pex1;
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile ccsr_pex_t *pex1 = &immap->im_pex1;
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
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uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
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uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
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if ((io_sel==2 || io_sel==3 || io_sel==5 \
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|| io_sel==6 || io_sel==7 || io_sel==0xF)
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
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debug ("PCI-EXPRESS 1: %s \n",
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pex1_agent ? "Agent" : "Host");
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debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
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if (pex1->pme_msg_det) {
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pex1->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",
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pex1->pme_msg_det);
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}
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debug ("\n");
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} else {
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printf ("PCI-EXPRESS 1: Disabled\n");
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}
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if ((io_sel == 2 || io_sel == 3 || io_sel == 5
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|| io_sel == 6 || io_sel == 7 || io_sel == 0xF)
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
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debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
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debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
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if (pex1->pme_msg_det) {
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pex1->pme_msg_det = 0xffffffff;
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debug(" with errors. Clearing. Now 0x%08x",
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pex1->pme_msg_det);
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}
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debug ("\n");
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} else {
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puts("PCI-EXPRESS 1: Disabled\n");
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}
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#else
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printf("PCI-EXPRESS1: Disabled\n");
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puts("PCI-EXPRESS1: Disabled\n");
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#endif
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return 0;
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@ -98,7 +97,6 @@ long int
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initdram(int board_type)
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{
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long dram_size = 0;
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extern long spd_sdram (void);
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram ();
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@ -110,7 +108,7 @@ initdram(int board_type)
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puts(" DDR: ");
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return dram_size;
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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@ -130,7 +128,7 @@ int testdram(void)
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf("SDRAM test phase 1:\n");
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puts("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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@ -141,7 +139,7 @@ int testdram(void)
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}
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}
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printf("SDRAM test phase 2:\n");
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puts("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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@ -152,7 +150,7 @@ int testdram(void)
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}
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}
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printf("SDRAM test passed.\n");
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puts("SDRAM test passed.\n");
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return 0;
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}
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#endif
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@ -177,9 +175,9 @@ long int fixed_sdram(void)
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ddr->sdram_mode_1 = CFG_DDR_MODE_1;
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ddr->sdram_mode_2 = CFG_DDR_MODE_2;
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ddr->sdram_interval = CFG_DDR_INTERVAL;
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ddr->sdram_data_init = CFG_DDR_DATA_INIT;
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ddr->sdram_data_init = CFG_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
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ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
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ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
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ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
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#if defined (CONFIG_DDR_ECC)
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@ -187,7 +185,7 @@ long int fixed_sdram(void)
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ddr->err_sbe = 0x00ff0000;
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#endif
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asm("sync;isync");
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udelay(500);
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#if defined (CONFIG_DDR_ECC)
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@ -198,7 +196,7 @@ long int fixed_sdram(void)
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ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
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#endif
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asm("sync; isync");
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udelay(500);
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#endif
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return CFG_SDRAM_SIZE * 1024 * 1024;
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@ -251,13 +249,12 @@ ft_board_setup(void *blob, bd_t *bd)
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int len;
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ft_cpu_setup(blob, bd);
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p = ft_get_prop(blob, "/memory/reg", &len);
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if (p != NULL) {
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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}
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#endif
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@ -269,86 +266,96 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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ulong val;
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ulong corepll;
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if (argc > 1) {
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cmd = argv[1][1];
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switch (cmd) {
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case 'f': /* reset with frequency changed */
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if (argc < 5)
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goto my_usage;
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/*
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* No args is a simple reset request.
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*/
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if (argv <= 0) {
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out8(PIXIS_BASE + PIXIS_RST, 0);
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/* not reached */
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}
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cmd = argv[1][1];
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switch (cmd) {
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case 'f': /* reset with frequency changed */
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if (argc < 5)
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goto my_usage;
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read_from_px_regs(0);
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val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
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corepll = strfractoint(argv[3]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
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if (val == 3) {
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puts("Setting registers VCFGEN0 and VCTL\n");
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read_from_px_regs(1);
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puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
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set_px_go();
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} else
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goto my_usage;
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while (1); /* Not reached */
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case 'l':
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if (argv[2][1] == 'f') {
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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/* reset with frequency changed */
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val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
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val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
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corepll = strfractoint(argv[3]);
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corepll = strfractoint(argv[4]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
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val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10));
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if (val == 3) {
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printf("Setting registers VCFGEN0 and VCTL\n");
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puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs(1);
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printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
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set_px_go();
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read_from_px_regs_altbank(1);
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puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
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set_px_go_with_watchdog();
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} else
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goto my_usage;
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while (1); /* Not reached */
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while(1); /* Not reached */
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case 'l':
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if (argv[2][1] == 'f') {
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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/* reset with frequency changed */
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val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
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} else if(argv[2][1] == 'd'){
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/*
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* Reset from alternate bank without changing
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* frequencies but with watchdog timer enabled.
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
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set_px_go_with_watchdog();
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while(1); /* Not reached */
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corepll = strfractoint(argv[4]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10));
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if (val == 3) {
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printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs(1);
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read_from_px_regs_altbank(1);
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printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
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set_px_go_with_watchdog();
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} else
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goto my_usage;
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while(1); /* Not reached */
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} else if(argv[2][1] == 'd'){
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/* Reset from next bank without changing frequencies but with watchdog timer enabled */
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
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set_px_go_with_watchdog();
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while(1); /* Not reached */
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} else {
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/* Reset from next bank without changing frequency and without watchdog timer enabled */
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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if(argc > 2)
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goto my_usage;
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printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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printf("Resetting board to boot from the other bank....\n");
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set_px_go();
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}
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default:
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goto my_usage;
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} else {
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/*
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* Reset from next bank without changing
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* frequency and without watchdog timer enabled.
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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if(argc > 2)
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goto my_usage;
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puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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puts("Resetting board to boot from the other bank....\n");
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set_px_go();
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}
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my_usage:
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printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
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printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
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printf("For example: reset cf 40 2.5 10\n");
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printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
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return;
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default:
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goto my_usage;
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}
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} else
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out8(PIXIS_BASE+PIXIS_RST,0);
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my_usage:
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puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
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puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
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puts(" reset altbank [wd]\n");
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puts("For example: reset cf 40 2.5 10\n");
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puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
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}
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@ -1,6 +1,6 @@
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/*
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* Copyright 2004 Freescale Semiconductor
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* Jeff Brown (jeffrey@freescale.com)
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* Copyright 2006 Freescale Semiconductor
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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@ -55,8 +55,7 @@ int checkcpu (void)
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minor = PVR_MIN(pvr);
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puts("CPU:\n");
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printf(" Core: ");
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puts(" Core: ");
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switch (ver) {
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case PVR_VER(PVR_86xx):
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@ -112,11 +111,11 @@ int checkcpu (void)
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printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
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}
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printf(" L2: ");
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puts(" L2: ");
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if (get_l2cr() & 0x80000000)
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printf("Enabled\n");
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puts("Enabled\n");
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else
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printf("Disabled\n");
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puts("Disabled\n");
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return 0;
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}
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@ -125,7 +124,6 @@ int checkcpu (void)
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static inline void
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soft_restart(unsigned long addr)
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{
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#ifndef CONFIG_MPC8641HPCN
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/* SRR0 has system reset vector, SRR1 has default MSR value */
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@ -137,8 +135,11 @@ soft_restart(unsigned long addr)
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__asm__ __volatile__ ("rfi");
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#else /* CONFIG_MPC8641HPCN */
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out8(PIXIS_BASE+PIXIS_RST,0);
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out8(PIXIS_BASE + PIXIS_RST, 0);
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#endif /* !CONFIG_MPC8641HPCN */
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while(1); /* not reached */
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}
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@ -149,10 +150,10 @@ soft_restart(unsigned long addr)
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void
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do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong addr;
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#ifndef CONFIG_MPC8641HPCN
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#ifdef CFG_RESET_ADDRESS
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addr = CFG_RESET_ADDRESS;
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ulong addr = CFG_RESET_ADDRESS;
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#else
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/*
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* note: when CFG_MONITOR_BASE points to a RAM address,
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@ -160,11 +161,9 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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* address. Better pick an address known to be invalid on your
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* system and assign it to CFG_RESET_ADDRESS.
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*/
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addr = CFG_MONITOR_BASE - sizeof (ulong);
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ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
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#endif
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#ifndef CONFIG_MPC8641HPCN
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/* flush and disable I/D cache */
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__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
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__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
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