SMBIOS tables only support 32bit addresses. If we don't have memory here
handle the error gracefully:
* on x86_64 fail to start U-Boot
* during UEFI booting ignore the missing table
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is a revert of a recent logic change in setup_zimage(). We do
actually need to install this information always. Change it to install
from the Coreboot tables if available, else the normal source.
Fixes: e7bae8283f ("x86: Allow installing an e820 when booting from coreboot")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
All the x86 devicetree files are built at once, whichever board is
actually being built. If coreboot is the target build, CONFIG_ROM_SIZE
is not defined and samus cannot build Chromium OS verified boot. Add
this condition to avoid errors about CONFIG_ROM_SIZE being missing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple
coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be
defined TARGET_COREBOOT.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a function comment for get_coreboot_info() and a declaration for
cb_get_sysinfo(), since this may be called from elsewhere.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.
If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These constants conflict with error codes returned by the MP
implementation when something is wrong. In particular, mp_first_cpu()
returns MP_SELECT_BSP when running without multiprocessing enabled.
Since this is -2, it is interpreted as an error by callers, which
expect a positive CPU number for the first CPU.
Correct this by using a different range for the pre-defined CPU
numbers, above zero and out of the range of possible CPU values. For
now it is safe to assume there are no more than 64K CPUs.
This fixes the 'mtrr' command when CONFIG_SMP is not enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When starting U-Boot from a previous-stage bootloader we presumably don't
need to set up the variable MTRRs. In fact this could be harmful if the
existing settings are not what U-Boot uses.
Skip that step in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With x86 we can execute an option ROM either natively or using the
x86 emulator (if enabled with CONFIG_BIOSEMU). Both of these share
the _X86EMU_env variable, with the native code using it to hold
register state during interrupt processing.
At present, in 32-bit U-Boot, the variable is declared twice, once
in common code and once in code only compiled with CONFIG_BIOSEMU.
With GCC 11 this causes a 'multiple definitions' error on boards
with CONFIG_BIOSEMU.
Drop the emulator definition when CONFIG_BIOSEMU is used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
When we do not have bootstage enabled, rather than include an empty
dummy function, we just don't reference it. This saves us space in some
tight builds. This also shows a few cases where show_boot_progress was
incorrectly guarded before.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
When switching to kernel.org x86_64 gcc 11.1.0 toolchain, u-boot.rom
built from qemu-x86_defconfig no longer boots anymore. Investigation
shows that U-Boot fails at a very early stage during the boot process,
in fdtdec_prepare_fdt() where fdt_check_header() complains that there
is not a valid device tree found at gd->fdt_blob which points to _end.
Now _end points to an allocated section .note.gnu.property which of
course is wrong.
This issue is however not seen when using the default Ubuntu 20.04 gnu
toolchain (gcc 9.3.0 with binutils 2.34). Further investigation shows
that it is caused by a behavior change of binutils v2.36 which is part
of the kernel.org gcc 11.1.0 toolchain, via the following commit:
939b95c77bf2 ("Linux/x86: Configure gas with --enable-x86-used-note by default")
In fact, there was already a regression bug report [1] for binutils two
months ago, but the binutils folks did not think it is a bug :(
To resolve this, there are several options:
* pass -Wa,-mx86-used-note=no to gas
* pass -R .note.gnu.property to objcopy
* discard the section in the linker script
Linux kernel uses the discard way [2], so let's do the same for U-Boot.
[1] https://sourceware.org/bugzilla/show_bug.cgi?id=27753
[2] commit 4caffe6a28d3 ("x86/vdso: Discard .note.gnu.property sections in vDSO")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit does the same thing as Linux commit 33def8498fdd.
Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.
Remove the quote operator # from compiler_attributes.h __section macro.
Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for stack protector for UBOOT, SPL, and TPL
as well as new pytest for stackprotector
Signed-off-by: Joel Peshkin <joel.peshkin@broadcom.com>
Adjust UEFI build flags.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The current usage of the variable CFLAGS_NON_EFI on the x86 architecture
deviates from other architectures.
Variable CFLAGS_NON_EFI is the list of compiler flags to be removed when
building UEFI applications. It is not a list of flags to be added anywhere.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Fix copy/paste errors in the descriptions of mtrr_close () and mtrr_set().
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We move qfw into its own uclass and split the PIO functions into a
specific driver for that uclass. The PIO driver is selected in the
qemu-x86 board config (this covers x86 and x86_64).
include/qfw.h is cleaned up and documentation added.
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Provide the model information through sysinfo so that it shows up on
boot. For memconfig 4 pins are provided, for 16 combinations. For SKU
ID there are two options:
- two pins provided in a ternary arrangement, for 9 combinations.
- reading from the EC
Add a binding doc and drop the unused #defines as well.
Example:
U-Boot 2021.01-rc5
CPU: Intel(R) Celeron(R) CPU N3450 @ 1.10GHz
DRAM: 3.9 GiB
MMC: sdmmc@1b,0: 1, emmc@1c,0: 2
Video: 1024x768x32 @ b0000000
Model: Google Coral (memconfig 5, SKU 3)
This depends on the GPIO series:
http://patchwork.ozlabs.org/project/uboot/list/?series=228126
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
The _SUPPORT suffix is from an earlier time and interferes with use of
the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix.
Tidy up the TODO that prompted this.
Signed-off-by: Simon Glass <sjg@chromium.org>
When booting from coreboot there is no need to notify the FSP of anything,
since coreboot has already done it. Nor it is possible, since the FSP
details are not provided by coreboot.
Skip it in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
When booting from coreboot the FSP video information is no-longer
available. Enable the coreboot driver so that we can get some sort of
display in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the debug UART is only set up in SPL, on the assumption that
the boot flow will always pass through there. When booting from coreboot,
SPL is not used, so the debug UART is not available.
Move the code into a common place so that it can be used in U-Boot proper
also. Add the required init to start_from_spl.S as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver cannot work when booted from coreboot, since the FSP
information is not available. Disable it in that case, so that the
coreboot video driver can be used instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move this code into a generic location so that it can be used by other x86
boards which want to boot from coreboot. Also ensure that this is called
if booting from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Quite a few new tag types have been added over the years. Bring these into
U-Boot so that all required tags can be parsed.
Add a proper comment to struct sysinfo_t while we are here, since many of
the meanings are not obvious.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is useful to be able to parse coreboot tables on any x86 build which is
booted from coreboot. Add a new Kconfig option to enable this feature and
move the code so it can be used on any board, if enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add new timestamp codes that are present in coreboot, so that we can decode
these in U-Boot.
At present TS_U_BOOT_START_KERNEL is used twice. It should only be used
just before jumping to Linux, so update the other call site to use
TS_START_KERNEL.
Signed-off-by: Simon Glass <sjg@chromium.org>
This all relates to the sysinfo structure provided by coreboot. Put the
timestamp definitions into the same file as the others. Tidy up a few
comments at the same time.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is possible to boot U-Boot for chromebook_coral either 'bare metal' or
from coreboot. In the latter case we want to provide access to the coreboot
sysinfo tables. Move the definitions into a file available to any x86
board.
Signed-off-by: Simon Glass <sjg@chromium.org>
In some cases CBFS does not start with a header but is just a collection
of files. It is possible to support this so long as the size of the CBFS
is provided.
Update the cbfs_init_mem() function to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since the recent bug fix, it doesn't matter which GPIO phandle is used so
long as the GPIO number is right. Still, we may as well use the correct
one to avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
At present the eMMC device does not have an alias so it appears after
the SD card which is device 1. There is no device 0 which is odd.
Make the eMMC device be the first one. Update the boot script to use the
new device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
We don't need to spell out the separate pieces of U-Boot phase binaries
anymore. Revert to using the simple entry and let binman do the expansion
itself as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
With Apollo Lake, SPL is placed in read-only memory. Set this new option
so that OF_PLATDATA_INST can be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
These devices are not actually built in TPL but are currently active in
the TPL devicetree. For of-platdata-inst this means that we will try to
generate devices for them, which fails.
Update them to be active only in U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
We don't normally need this driver in TPL/SPL, so drop it for now. It can
be enabled by individual boards if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
With TPL we don't need full PCI support and it adds to code size. Instead,
a simple_bus driver is good enough to be able to read and write the PCI
config and do a little basic setup.
So at present there are two drivers in U-Boot called pci_x86. One is in
UCLASS_PCI, used in SPL and U-Boot proper. The other is in
UCLASS_SIMPLE_BUS and used only in TPL.
Add a tag to tell dtoc about this, so it knows which one to use when
generating the devices and uclasses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
With the standard of-platdata we must fix up driver_data manually. With
of-platadata-inst this is not necessary, since it is added to the device
by dtoc.
Update the code to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This enum is needed to generate build-time devices. Tell dtoc where to
find the header, to avoid compile errors in the generated code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The dm.h header should come first. In fact it needs to, since otherwise
the driver model definitions are not available to dt-structs.h
Fix this, since it causes problems with OF_PLATDATA_INST.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Collect this together in one place, so driver model can access set it up
in a new place if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
At present most of the Intel-specific code is built on all devices, even
those which don't have software support for the features provided there.
This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does
not have the required features.
Add a new INTEL_SOC option to control this access. This must be selected
by SoCs that can support the required features.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in arch/x86/Kconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This option is better placed in the x86 code since it is not generic
enough to be in the core code. Move it.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in arch/x86/Kconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
When CONFIG_CHROMEOS is not enabled this currently does not build. Fix it.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Building qemu-x86_64_defconfig with GCC 11.0 fails with:
arch/x86/cpu/intel_common/lpc.c:
In function ‘lpc_common_early_init’:
arch/x86/cpu/intel_common/lpc.c:56:40:
error: expression does not compute the number of elements in this array;
element type is ‘struct reg_info’, not ‘u32’ {aka ‘unsigned int’}
[-Werror=sizeof-array-div]
56 | sizeof(values) / sizeof(u32));
| ^
arch/x86/cpu/intel_common/lpc.c:56:40: note: add parentheses around the
second ‘sizeof’ to silence this warning
arch/x86/cpu/intel_common/lpc.c:50:11: note: array ‘values’ declared here
50 | } values[4], *ptr;
| ^~~~~~
Add parentheses to silence warning.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't need to implement direction_input() and direction_output()
anymore. Drop them and use update_flags() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
