Commit graph

4249 commits

Author SHA1 Message Date
Wolfgang Denk
0cf207ec01 WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 09:08:16 -04:00
Wolfgang Denk
0a50b3c97b WS cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-30 08:08:56 -04:00
Wolfgang Denk
66356b4c06 WS cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 08:08:56 -04:00
Patrick Delaunay
6493fa4c3d arm: use CONFIG_SUPPORT_PASSING_ATAGS
Simplify the bootm and the spl code by using the new config
CONFIG_SUPPORT_PASSING_ATAGS.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-24 14:30:46 -04:00
Stefan Roese
4e062fc955 arm64: Kconfig: Enable usage of optimized memset/memcpy/memmove
This patch enables the use of the optimized memset(), memmove() &
memcpy() versions recently added on ARM64.

Please note that these optimized functions are now only enabled for
recent GCC versions (>= 9.4), as earlier GCC versions throw these
errors:

aarch64-linux-ar: warning: arch/arm/lib/memset-arm64.o: unsupported GNU_PROPERTY_TYPE (5) type: 0xc0000000
...

Signed-off-by: Stefan Roese <sr@denx.de>
[trini: Make this default to off as it causes problems on some platforms still]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-24 07:49:16 -04:00
Eugen Hristev
a6bbb8b596 ARM: at91: remove references to RM9200DK
The AT91 RM9200DK board was removed long time ago.
Remove existing references that were not cleaned up.

Fixes: 1c85752258 ("ARM: remove broken "at91rm9200dk" board")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-09-21 10:08:24 +03:00
Tom Rini
b9d66a061b imx: Convert SERIAL_TAG support to ENV_VARS_UBOOT_RUNTIME_CONFIG
No iMX platforms have supported ATAG-based booting.  They have however
re-used the CONFIG_SERIAL_TAG option as a way to enable support of
reading the OTP fuses and setting the serial# environment variable in
some cases.  Change the warp7 support to use this symbol, use this for
updating the rest of the imx7 code, and update the imx8 conditionals.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-07 13:04:52 -04:00
Tom Rini
0017931971 Revert most of the series for adding vexpress_aemv8r support
Per a request from Andre Przywara and agreed with by Peter Hoyes, the
vexpress aemv8r support wasn't quite ready to be merged, but the
discussion had moved off list.  We should keep the first patch in the
series for now, but revert the rest.  This reverts the following
commits:

e0bd6f31ce doc: Add documentation for the Arm vexpress board configs
30e5a449e8 arm: Use armv8_switch_to_el1 env to switch to EL1
b53bbca63b vexpress64: Add BASER_FVP vexpress board variant
2f5b7b7490 armv8: Add ARMv8 MPU configuration logic
37a757e227 armv8: Ensure EL1&0 VMSA is enabled

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-03 10:42:15 -04:00
Oleksandr Suvorov
7befc8490a psci: fix double declaration
The prototype of psci_features() duplicated. Remove extra declaration.

Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1")
Reported-by: Michael Scott <mike@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2021-09-02 11:19:58 -04:00
Peter Hoyes
2f5b7b7490 armv8: Add ARMv8 MPU configuration logic
Armv8r64 is the first Armv8 platform that only has a PMSA at the
current exception level. The architecture supplement for Armv8r64
describes new fields in ID_AA64MMFR0_EL1 which can be used to detect
whether a VMSA or PMSA is present. These fields are RES0 on Armv8a.

Add logic to read these fields and, for the protection of the memory
used by U-Boot, initialize the MPU instead of the MMU during init, then
clear the MPU regions before transition to the next stage.

Provide a default (blank) MPU memory map, which can be overridden by
board configurations.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-09-02 10:17:45 -04:00
Peter Hoyes
37a757e227 armv8: Ensure EL1&0 VMSA is enabled
On Armv8-R, the EL1&0 memory system architecture is configurable as a
VMSA or PMSA, and resets to an "architecturally unknown" value.

Add code to armv8_switch_to_el1_m which detects whether the MSA at
EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields.
If it is we must ensure the VMSA is enabled so that a rich OS can boot.

The MSA and MSA_FRAC fields are described in the Armv8-R architecture
profile supplement (section G1.3.7):
https://developer.arm.com/documentation/ddi0600/latest/

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-09-02 10:17:45 -04:00
Peter Hoyes
53b40e8d54 armv8: Disable pointer authentication traps for EL1
The use of ARMv8.3 pointer authentication (PAuth) is governed by fields
in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset
value of these fields is 'architecturally unknown' so we must ensure
that the fields are enabled (to disable the traps) if we are entering
the kernel at EL1.

The APK field disables PAuth instruction traps and the API field
disables PAuth register traps

Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing
so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer
authentication is supported by the hardware.

The runtime checks require a second temporary register, so add this to
the EL1 transition macro signature and update 2 call sites.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-09-02 10:17:45 -04:00
Tom Rini
a2ac2b964b Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SKIP_LOWLEVEL_INIT
   CONFIG_SKIP_LOWLEVEL_INIT_ONLY

In order to do this, we need to introduce SPL and TPL variants of these
options so that we can clearly disable these options only in SPL in some
cases, and both instances in other cases.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:47:49 -04:00
Tom Rini
5afdcca019 arm: Migrate GICV2 / GICV3 to Kconfig
Migrate CONFIG_GICV2 and CONFIG_GICV3 to Kconfig.  We still have the GIC
related registers that need to be handled more cleanly but start by
moving this symbol to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:13:26 -04:00
Tom Rini
52c7e37596 Convert CONFIG_SYS_I2C_EARLY_INIT to Kconfig
Convert SYS_I2C_EARLY_INIT to Kconfig, and make it depend on
SPL_SYS_I2C_LEGACY.  Remove the weak implementation as it's either
something that needs to exist for real, or shouldn't be called.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:07 -04:00
Tom Rini
55dabcc8f2 Convert CONFIG_SYS_I2C_LEGACY to Kconfig and add CONFIG_[ST]PL_SYS_I2C_LEGACY
First, we convert CONFIG_SYS_I2C_LEGACY to Kconfig.  Next, as you cannot
have SYS_I2C_LEGACY and DM_I2C at the same time, introduce
CONFIG_SPL_SYS_I2C_LEGACY so that we can enable the legacy option only
in SPL.  Finally, for some PowerPC cases we also need
CONFIG_TPL_SYS_I2C_LEGACY support.  Convert all of the existing users to
one or more symbols.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:07 -04:00
Peng Fan
3e23794181 imx8ulp: add upower api support
Add upower api support, this is modified from upower firmware exported
package.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Peng Fan
4b9423e6f2 imx8ulp: move struct mu_type to common header
Move struct mu_type to common header to make it reusable by upower and
S400

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Peng Fan
fdfa214acf arm: imx8ulp: add iomuxc support
Add i.MX8ULP iomuxc support

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Ye Li
619412ab54 arm: iMX8ULP: Add boot device relevant functions
Read from ROM API to get current boot device.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Peng Fan
3912d4b273 imx8ulp: unify rdc functions
Unify rdc function to rdc.c
Update soc.c to use new rdc function

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Peng Fan
367ff4bc84 arm: imx8ulp: add rdc support
There is xrdc inside i.MX8ULP, we need to configure permission to make
sure AP non-secure world could access the resources.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Ye Li
ba472a209b arm: imx8ulp: release and configure XRDC at early phase
Since S400 will set the memory of SPL image to R/X. We can't write
to any data in SPL image.

1. Set the parameters save/restore only for u-boot, not for SPL. to
   avoid write data.
2. Not use MU DM driver but directly call MU API to send release XRDC
   to S400 at early phase.
3. Configure the SPL image memory of SRAM2 to writable (R/W/X)

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Ye Li
26b53212b8 drivers: misc: s400_api: Update API for fuse read and write
Add API to support fuse read and write

Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09 14:46:51 +02:00
Ye Li
7aeaf4d9a6 drivers: misc: imx8ulp: Update S400 API for release RDC
The RDC API is updated to add a field for XRDC or TRDC

Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09 14:46:51 +02:00
Ye Li
6306f75d8e drivers: misc: imx8ulp: Add S400 API for image authentication
Add S400 API for image authentication

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Peng Fan
a84dab4f70 arm: imx8ulp: add clock support
Add i.MX8ULP clock support

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:51 +02:00
Ye Li
0c00d03aca driver: misc: Add MU and S400 API to communicate with Sentinel
Add MU driver and S400 API. Need enable MISC driver to work

Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09 14:46:50 +02:00
Ye Li
6f3858d732 arm: imx8ulp: add container support
i.MX8ULP support using ROM API to load container image,
it use same ROM API as i.MX8MN/MP, and use same container format
as i.MX8QM/QXP.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Ye Li
31f0085285 arm: imx8: Move container image header file to mach-imx
Since the container is shared among i.MX platforms, move its header file
to mach-imx

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
9ef89ea9b0 arm: imx: basic i.MX8ULP support
Add basic i.MX8ULP support

For the MMU part, Using a simple way the calculate the MMU size to avoid
default heavy calcaulation. And align address and size in the table
settings to 2MB or 4GB as much as possible. So we can reduce the 4K page
allocations in MMU table which will spends much time in create the
page table

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
77c3b9cc98 arm: imx8ulp: support print cpu info
Support print cpu info. the clock function has not been added, it will
be added in following patches.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
5f17fef893 arm: imx: sys_proto: move boot mode define to common header
These defines could be reused by i.MX8ULP, so move them
to common header.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
331d40d701 arm: imx: add i.MX8ULP cpu type and helper
Add i.MX8ULP cpu type and helpers.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Tom Rini
5371593aed Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi
- Move the PSCI runtime code for H3/A23/A33 into SRAM
- Pick the environment from the actual MMC boot device (SD card vs.
  eMMC)
- Plus a small improvement from Icenowy, just for good measure.
2021-07-31 20:51:24 -04:00
Samuel Holland
1ebfc0c631 sunxi: A23/A33/H3: Move sun8i secure monitor to SRAM A2
So far for the H3, A23, and A33 SoCs, we use DRAM to hold the secure
monitor code (providing PSCI runtime services). And while those SoCs do
not have the secure SRAM B like older SoCs, there is enough (secure)
SRAM A2 to put the monitor code and data in there instead.

Follow the design of 64-bit SoCs and use the first part for the monitor,
and the last 16 KiB for the SCP firmware. With this change, the monitor
no longer needs to reserve a region in DRAM.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: amend commit message, fix R40 and V3s build]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-08-01 00:11:34 +01:00
Patrice Chotard
268f6ac1f9 arm64: Update memcpy_{from, to}io() helpers
At early U-Boot stage, before relocation, MMU is not yet configured
and disabled. DDR may not be configured with the correct memory
attributes (can be configured in MT_DEVICE instead of MT_MEMORY).

In this case, usage of memcpy_{from, to}io() may leads to synchronous
abort in AARCH64 in case the normal memory address is not 64Bits aligned.

To avoid such situation, forbid usage of normal memory cast to (u64 *) in
case MMU is not enabled.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: mark.kettenis@xs4all.nl
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-28 19:30:22 -04:00
Simon Glass
69d9eda4da i2c: Rename CONFIG_SYS_I2C to CONFIG_SYS_I2C_LEGACY
It is quite confusing that CONFIG_SYS_I2C selects the legacy I2C and
CONFIG_DM_I2C selects the current I2C. The deadline to migrate I2C is less
than a year away.

Also we want to have a CONFIG_I2C for U-Boot proper just like we have
CONFIG_SPL_I2C for SPL, so we can simplify the Makefile rules.

Rename this symbol so it is clear it is going away.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-28 14:29:37 -04:00
Peter Hoyes
c48fec6e7c armv8: Initialize CNTFRQ if at highest exception level
CNTFRQ_EL0 is only writable from the highest supported exception
level on the platform. For Armv8-A, this is typically EL3, but
technically EL2 and EL3 are optional so it may need to be
initialized at EL2 or EL1. For Armv8-R, the highest exception
level is always EL2.

This patch moves the initialization outside of the switch_el
block and uses a new macro branch_if_not_highest_el which
dynamically detects whether it is at the highest supported
exception level.

Linux's docs state that CNTFRQ_EL0 should be initialized by the
bootloader. If not set, the the U-Boot prompt countdown hangs.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-07-23 18:53:46 -04:00
Tom Rini
83befb4466 Merge tag 'ti-v2021.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Enabled distro boot for all TI platforms.
- Cleanup for AM335x Guardian Board
- PRUSS rproc on AM65 platform.
- Add PMIC support for J7200
- Misc fixes for Nokia RX-51

# Conflicts:
#	arch/arm/mach-omap2/am33xx/Kconfig
2021-07-19 08:29:24 -04:00
Tom Rini
d5dbc661c3 i.MX
----
 
 - mx7ulp : fix  WDOG
 - imx8 : Phytec
 - USB3 support for i.MX8
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCYPLjyA8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76aBtgCfUI2SbFwh7oydllrwb0lEvWegfNcAn1JpR3Zn
 H41xrXQqCBedYKxvuUUL
 =5wvR
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX
----

- mx7ulp : fix  WDOG
- imx8 : Phytec
- USB3 support for i.MX8

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17 10:52:21 -04:00
Ye Li
4a837d433c arm: imx8mq: Add USB clock init function
Add clock function to setup relevant clocks for USB3.0 controllers and
PHYs on i.MX8MQ

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se>
2021-07-17 13:12:23 +02:00
Adam Ford
46bf58d9f6 arm: omap3: Make secureworld_exit() static
secureworld_exit() is only used in one file, so make it static
to that file and remove it from sys_proto.h. This
may help with some further optimization in the future.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210625192308.277136-3-aford173@gmail.com
2021-07-15 17:56:04 +05:30
Adam Ford
1ddd0ed34a arm: omap3: Make try_unlock_memory() static
try_unlock_memory() is only used in one file, so make it static
in that file,remove it from the sys_proto header file, and relocate
it into the #ifdef section that call it. This will make it only built
under the conditions when it is called, and it may help with some
further optimization in the future.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210625192308.277136-2-aford173@gmail.com
2021-07-15 17:56:04 +05:30
Moses Christopher
050531db00 am335x, guardian: mem: Add board dependent mem values
- Add mem-guardian.h derived from am33xx/mem.h

    * Add GPMC config values optimized for Bosch Guardian Board
    * NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA

Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210611161350.2141-3-Gireesh.Hiremath@in.bosch.com
2021-07-15 17:56:03 +05:30
Tim Harvey
c1f6fd2bb7 pci: imx: use reset-gpios if defined by device-tree
If reset-gpio is defined by device-tree use that if
CONFIG_PCIE_IMX_PERST_GPIO is not defined.

Note that after this the following boards which define
CONFIG_PCIE_IMX_PERST_GPIO in their board header file as well as their
device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without
consequence:
 - mx6sabresd
 - mx6sxsabresd
 - novena
 - tbs2910
 - vining_2000

Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_PERST_GPIO and does
not have reset-gpios defined it it's pcie node in the dt thus removing
CONFIG_PCIE_IMX_PERST_GPIO globally can't be done until that board adds
reset-gpios.

Cc: Ian Ray <ian.ray@ge.com> (maintainer:GE BX50V3 BOARD)
Cc: Sebastian Reichel <sebastian.reichel@collabora.com> (maintainer:GE BX50V3 BOARD)
Cc: Fabio Estevam <festevam@gmail.com> (maintainer:MX6SABRESD BOARD)
Cc: Marek Vasut <marex@denx.de> (maintainer:NOVENA BOARD)
Cc: Soeren Moch <smoch@web.de> (maintainer:TBS2910 BOARD)
Cc: Silvio Fricke <open-source@softing.de> (maintainer:VINING_2000 BOARD)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10 16:53:34 +02:00
Andre Przywara
9faae5457f mmc: sunxi: Increase MMIO FIFO read performance
To avoid the complexity of DMA operations (with chained descriptors), we
use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us
to drain or fill the MMC data buffer FIFO very easily.

However those MMIO accesses are somewhat costly, so this limits our MMC
performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6
(partly due to the lower AHB1 frequency).

As it turns out we read the FIFO status register after *every* word we
read or write, which effectively doubles the number of MMIO accesses,
thus effectively more than halving our performance.

To avoid this overhead, we can make use of the FIFO level bits, which are
in the very same FIFO status registers.
So for a read request, we now can collect as many words as the FIFO
level originally indicated, and only then need to update the status
register.

We don't know for sure the size of the FIFO (and it seems to differ
across SoCs anyway), so writing is more fragile, which is why we still
use the old method for that. If we find a minimum FIFO size available on
all SoCs, we could use that, in a later optimisation.

This patch increases the eMMC read speed on a Pine64-LTS from about
22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s
we now reach the practical limit for 3.3V SD cards.
On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Andre Przywara
937ee31e32 mmc: sunxi: Fix MMC clock parent selection
Most Allwinner SoCs which use the so called "new timing mode" in their
MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their
parent input clock. This is interestingly enough compensated by a hidden
"by 2" post-divider in the mod clock, so the divider and actual output
rate stay the same.

Even though for the H6 and H616 (but only for them!) we use the doubled
input clock for the divider computation, we never accounted for the
implicit post-divider, so the clock was only half the speed on those SoCs.
This didn't really matter so far, as our slow MMIO routine limits the
transfer speed anyway, but we will fix this soon.

Clean up the code around that selection, to always use the normal PLL6
(PERIPH0(1x)) clock as an input. As the rate and divider are the same,
that makes no difference.
Explain the hardware differences in a comment.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Andre Przywara
f9d1324775 sunxi: clock: H6/H616: Fix PLL clock factor encodings
Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.

This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000

Also the CPU frequency (PLL1) was a tad too high before.

For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code
itself, not in the bit field macro. Move this there to be aligned with
what the other SoCs and other PLLs do.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2021-07-10 01:22:09 +01:00
Tom Rini
570c3dcfc1 arm: Remove spear600 boards and the rest of SPEAr support
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.  As this is
the last of the SPEAr platforms, so remove the rest of the remaining
support as well.

Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00