Commit graph

124 commits

Author SHA1 Message Date
Thomas Chou
038be18fd9 nios2: add 3c120 and 10m50 devboards MAINTAINERS
Add 3c120 and 10m50 devboards MAINTAINERS

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-11-12 08:26:59 +08:00
Thomas Chou
6168dc6a7a nios2: zap nios2-generic board dir
As we use device tree to control u-boot now, the generic
board can be removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-10-23 14:55:36 +08:00
Thomas Chou
bbba0714b7 nios2: zap initdram
Zap initdram(), as it is not used.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-10-23 07:37:20 +08:00
Thomas Chou
ca844dd8c5 nios2: convert altera sysid to driver model
Convert altera sysid to driver model with misc uclass.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-10-23 07:37:03 +08:00
Thomas Chou
88d5ecf4b9 nios2 : convert altera_pio to driver model
Convert altera_pio to driver model.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-10-23 07:37:03 +08:00
Thomas Chou
b6c180928c nios2: move altera_pio_init to board_early_init_r
As altera_pio_init() uses BSS, it should be moved to
board_early_init_r().

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-10-23 07:28:37 +08:00
Dinh Nguyen
4348f36bbb arm: socfpga: update MAINTAINERS' file for cyclone5_socdk and arria5_socdk
commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files"
renames the configs files, so we should update the MAINTAINERS' entry. At
the same time, update the email for Dinh Nguyen.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-23 03:55:28 +02:00
Marek Vasut
29aa439759 arm: socfpga: Fix ArriaV SoCDK PLL config
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:21 +02:00
Marek Vasut
d418301167 arm: socfpga: Fix MAINTAINERS entry for CV/AV SoCDK
Repair the maintainer entries so they match the current state of code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
cc9429a556 arm: socfpga: Make the pinmux table const u8
Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
f6badb0d89 arm: socfpga: Switch to filtered QTS files
Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
37b3a30ae6 arm: socfpga: Remove AV-specific parts from CV-SoCDK
Just remove the ArriaV specific parts from the CycloneV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
c68eea0492 arm: socfpga: Remove CV-specific parts from AV-SoCDK
Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
f089240128 arm: socfpga: Split Altera socfpga into AV and CV SoCDK
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.

On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.

Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
ca62d2e1fc arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Dinh Nguyen
cf96848bc7 ddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKS
Fix build error for socfpga_cyclone5_defconfig:

board/altera/socfpga/wrap_sdram_config.c:245:26: error: ‘RW_MGR_MEM_NUMBER_OF_RANKS’ undeclared here (not in a function)
make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:30 +02:00
Marek Vasut
042ff2d0fa ddr: altera: sequencer: Wrap misc remaining macros
Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
10c14261f3 ddr: altera: sequencer: Wrap IO_* macros
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
d718a26b0c ddr: altera: sequencer: Wrap RW_MGR_* macros
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
04955cf247 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init
Introduce two wrapper functions, socfpga_get_seq_ac_init() and
socfpga_get_seq_inst_init() to avoid direct inclusion of the
sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS
generated files. This reduces namespace pollution again.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:28 +02:00
Marek Vasut
9c76df518c ddr: altera: sequencer: Move qts-generated files to board dir
Move the files generated by QTS into the board directory, they should not
be part of the driver files at all.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:28 +02:00
Marek Vasut
5af914189e ddr: altera: sdram: Introduce socfpga_sdram_get_config()
Introduce socfpga_sdram_get_config() function implement in a board file,
which returns the socfpga_sdram_config structure. This is the last step
in cleaning up the socfpga_mmr_init_full(), but not the last step which
allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c
thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
2d779b39b4 arm: socfpga: system: Clean up pinmux_config.c
Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux
table and it's size from the QTS-generated pinmux_config.c. The target
here is again to get rid of poluting global namespace by including the
pinmux_config.h into it.

Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros,
which are explicitly useless to us in U-Boot. Instead, U-Boot does
use DT to detect exactly these configuration options. This patch
makes sure that while this QTS-generated file can stay in the tree,
these obscure macros do not ooze into the namespace anymore.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:07 +02:00
Marek Vasut
575d741516 arm: socfpga: scan: Zap iocsr_scan_chain*_table()
Introduce accessor iocsr_get_config_table() for retrieving IOCSR config
tables. This patch is again trimming down the namespace polution.

The IOCSR config tables are used only by scan manager, they are generated
by qts and are board specific. Before this patch, the approach to use
these tables in scan manager was to define an extern variable to silence
the compiler and compile board-specific iocsr_config.c into U-Boot which
defined those extern variables. Furthermore, since these are tables and
the scan manager needs to know the size of those tables, iocsr_config.h
is included build-wide.

This patch wraps all this into a single accessor which takes the scan
chain ID and returns pointer to the table and it's size. All this is
wrapped in wrap_iocsr_config.c board-specific file. The file includes
the iocsr_config.c (!) to access the original tables and transitively
iocsr_config.h . It is thus no longer necessary to include iocsr_config.h
build-wide and the namespace polution is trimmed some more.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:07 +02:00
Marek Vasut
93b4abd3a2 arm: socfpga: clock: Clean up pll_config.h
Extract the clock configuration horribleness caused by pll_config.h in
the following manner.

First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.

The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.

The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Marek Vasut
d04941cf33 arm: socfpga: Move sdram_config.h to board dir
This file is absolutelly positively board specific, so move it
into the correct place.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:05 +02:00
Marek Vasut
9617ceb9cf arm: socfpga: Move generated files into qts subdir
Move all the files generated by Quartus into the qts/ subdir of the
board/altera/socfpga dir to make them explicitly separate from the
generic U-Boot code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:04 +02:00
Masahiro Yamada
7865f4b0b6 ARM: socfpga: move board select into mach-socfpga/Kconfig
Switch to a more standard way of board select; put the SoC select
into arch/arm/Kconfig and move the board select menu under
arch/arm/mach-socfpga/Kconfig.

Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-07 05:21:08 +02:00
Masahiro Yamada
cc25d85be3 ARM: socfpga: do not add board directory to header search path
The compiler option "-Iboard/$(VENDOR)/$(BOARD)" just exists here
for iocsr_config.c to be able to include iocsr_config.h.

Use "..." instead of <...> to include a header in the same directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-07 05:19:29 +02:00
Dinh Nguyen
8b73dda86b arm: socfpga: spl: update peripheral pll for dev kit
"commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration"
mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct
value should be 79.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
a74732b611 arm: socfpga: spl: Add s_init stub
Add a stub s_init function in the board file. The reason why the stub function
is needed is that most of the work is now being done in board_init_f(), there
is no need for the SPL to do anything s_init(). However, since lowlevel_init()
is still branching to s_init(), we need stub function for now, until
lowlevel_init() morphs into s_init().

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
3c38de5464 arm: socfpga: fix uart0 pin mux configuration
commit "07d30b6c3129 arm: socfpga: Sync Cyclone V DK pinmux configuration"
incorrectly set the muxing for UART0 on the Cyclone V DK.

This fixes it up so UART0 is working again.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Marek Vasut
c115a0d4e7 arm: socfpga: Add Altera Arria V DK support
Add support for the Altera Arria V development kit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-03-04 23:07:04 +01:00
Marek Vasut
d7a73038f5 arm: socfpga: Zap board_early_init_f()
Zap this unused empty function, no point in having it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-03-04 23:07:04 +01:00
Marek Vasut
7287d5f091 arm: socfpga: Zap checkboard()
Since all boards now have a DT, instead of hard-coding the board
name into the U-Boot binary, read the board name from DT "model"
property.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-03-04 23:07:04 +01:00
Marek Vasut
758be453de arm: socfpga: Drop cyclone5 suffix from board file name
Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file
will contain Arria 5 support as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-03-04 23:07:04 +01:00
Marek Vasut
0d13a0051b arm: socfpga: Sync Cyclone V DK PLL configuration
Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

NOTE: This change is useless until we get proper SPL support, at
      which point this will likely need further rework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-03-04 23:07:04 +01:00
Marek Vasut
a2d96abe39 arm: socfpga: Sync Cyclone V DK pinmux configuration
Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-03-04 23:07:04 +01:00
Marek Vasut
12ec3c648e arm: socfpga: Minor coding style fix
Replace multiple spaces with a single tab.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-03-04 23:07:03 +01:00
Pavel Machek
065496d1b5 arm: socfpga: board: Repair Micrel PHY tuning
Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Pavel Machek <pavel@denx.de>
2014-12-16 15:32:14 +01:00
Dinh Nguyen
74ae12e184 arm: socfpga: set skew settings for ethernet phy
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5
hardware.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
2014-12-06 13:51:54 +01:00
Stefan Roese
fa8278d702 arm: socfpga: Add myself as maintainer for the SoCrates board
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-06 13:51:54 +01:00
Marek Vasut
0223a95c72 arm: socfpga: Add example UDC config
Add example of an USB UDC configuration with DFU and UMS.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2014-11-07 16:32:02 +01:00
Georges Savoundararadj
2e07c249a6 kconfig: arm: introduce symbol for ARM CPUs
This commit introduces a Kconfig symbol for each ARM CPU:
CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136,
CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100.
Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected
for CPU_ARM1176 and CPU_V7.

For each target, the corresponding CPU is selected and the definition of
SYS_CPU in the corresponding Kconfig file is removed.

Also, it removes redundant "string" type in some Kconfig files.

Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-10-29 09:02:09 -04:00
Marek Vasut
4ab333b765 arm: socfpga: Move cache_enable to CPU code
Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:46:51 +02:00
Marek Vasut
40e7bcdee7 arm: socfpga: cache: Enable D-Cache
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:46:50 +02:00
Marek Vasut
604364e42c arm: socfpga: board: Align checkboard() output
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:46:50 +02:00
Pavel Machek
868749a61d arm: socfpga: board: Correctly set ATAG position
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
2014-10-06 17:46:50 +02:00
Marek Vasut
0911af00b0 arm: socfpga: clock: Add missing stubs into board file
Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:46:48 +02:00
Masahiro Yamada
461be2f96e kconfig: remove redundant "string" type in arch and board Kconfigs
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.

We can delete the ones in arch and board Kconfig files.

This commit can be easily reproduced by the following command:

find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
    N
    s/\n[[:space:]]*string//
}
'

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-13 16:43:55 -04:00