Commit graph

82132 commits

Author SHA1 Message Date
Simon Glass
eb6e903a56 test: Detect a change in the device tree
If the device tree changes during a test and we cannot restore it, mark
it as such so that future tests which need the live tree are skipped.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:09:56 -04:00
Simon Glass
0e4b697f88 test: Make a copy of the device tree before running a test
When the flat device tree changes it can mess up the live tree since that
uses the flat tree for its strings. This affects only a few sandbox tests
which modify the device tree, but the number will grow as ofnode support
for writing improves.

While the control FDT is not intended to change while U-Boot is running,
some tests do so. For example, the ofnode interface only supports
modifying properties in the control FDT, so tests must use that.

To solve this problem, keep a copy of the FDT and restore it as needed
when the test is finished. The copy only happens on sandbox (except SPL
builds), to reduce memory usage and because these tests are not useful on
other boards. For other boards, a checksum is taken to ensure that nothing
changes.

It would be possible to always checksum the FDT on sandbox and only
restore it if needed, but this is slightly slower than restoring it every
time, at least with crc8.

Move the code which checks for success to the very end, for clarity.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:09:56 -04:00
Simon Glass
9830698765 dm: core: Drop the const from ofnode
Now that we support writing to ofnodes, the const is not accurate. Drop
it to avoid undesirable casting.

Also drop the ofnode_to_npw() which is now the same as ofnode_to_np().

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
c3a194dec9 dm: core: Support writing a property to an empty node
At present this does not work with livetree. Fix it and add a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
ffe9039249 dm: core: Allow adding ofnode subnodes
Add this feature to the ofnode interface, supporting both livetree and
flattree. If the node exists it is returned, along with a -EEXIST error.
Update the functions it calls to handle this too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
5ecba3ba40 dm: core: Document the livetree structures properly
Clarify the data structure so it is easier for people to understand,
particularly the corner cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
62d638386c test: Support testing malloc() failures
It is helpful to test that out-of-memory checks work correctly in code
that calls malloc().

Add a simple way to force failure after a given number of malloc() calls.

Fix a header guard to avoid a build error on sandbox_vpl.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-09-29 16:07:58 -04:00
Simon Glass
7c14dc7f77 test: Fix missing livetree test runs
At present the live tree tests are not run on sandbox. This bug is in two
parts, with a duplicate flag value and incorrect logic in the test runner.
This was not noticed because the bug was fixed in a later commit and does
not cause test failures.

Fix this.

Fixes: 7b1dfc9fd7 ("dm: core: Prepare for updating the device tree with ofnode")

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
b215b6034c event: Pass the images to EVT_FT_FIXUP
Pass the boot images along as well, in case the fixups need to look at
them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
829d51246f dm: core: Pass a root node to of_find_node_by_phandle()
This function currently assumes that the control FDT is used. Update it
to allow a root node to be passed, so it can work with any tree.

Also add a comment to ofnode_get_by_phandle() so that its purpose is
clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:58 -04:00
Simon Glass
b5001cb4bd event: Allow multiple spy declarations for each event
At present only one spy is allowed per event. Update the naming to allow
more than one, since some need this flexibility, e.g. the EVT_FT_FIXUP
event.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Simon Glass
f39e5b802a event: Fix a typo in the EVENT help
Fix the help message.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Simon Glass
96d0c4514f sandbox: power: Update PMIC driver to use log
Use the log functions instead of pr_...() so we can avoid using __func__.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-09-29 16:07:57 -04:00
Simon Glass
b7f134eece log: update the comment for log_msg_ret()
Add some advice on string size here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Simon Glass
f3543e6944 treewide: Drop image_header_t typedef
This is not needed and we should avoid typedefs. Use the struct instead
and rename it to indicate that it really is a legacy struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Simon Glass
da79b2f25e treewide: Drop image_info_t typedef
This is not needed and we should avoid typedefs. Use the struct instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Simon Glass
d9d7c20b73 treewide: Drop bootm_headers_t typedef
This is not needed and we should avoid typedefs. Use the struct instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Simon Glass
c56b2bb9b9 image: Fix BOOTM_STATE values
Tidy up the code style for these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Tom Rini
97c0a9c570 Merge branch '2022-09-29-assorted-fixes'
- Assorted fixes we want to include before the release.
2022-09-29 16:06:19 -04:00
Pierre-Clément Tosi
76f921eb95 board_r: Relocate OF_EMBED if NEEDS_MANUAL_RELOC only
When the embedded device tree is pointed to by the __dtb_dt_*begin
symbols, it seems to be covered by the early relocation code and doesn't
need to be manually patched.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
2022-09-29 10:10:39 -04:00
Pali Rohár
d21bbb98cc pci: Remove duplicate PCI_REGION_IO / "io" line
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-29 10:10:39 -04:00
Miaoqian Lin
316590db29 tools: env: Fix missing closedir in ubi_get_volnum_by_name
The function calls opendir() but missing the corresponding
closedir() before exit the function.
Add missing closedir() to fix it.

Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
2022-09-29 10:10:39 -04:00
Nishanth Menon
d2ab2a2baf board: ti: common: board_detect: Fix EEPROM read quirk for AM6 style data
The situation is similar to commit bf6376642f ("board: ti: common:
board_detect: Fix EEPROM read quirk"). This is seen on a variant of
eeproms seen on some BeagleBone-AI64 which now has a mix of both 1 byte
addressing and 2 byte addressing eeproms.

Unlike the am335x (ti_i2c_eeprom_am_get) and dra7
(ti_i2c_eeprom_dra7_get) which use constant data structure which allows
us to do a complete read of the data, the
am6(ti_i2c_eeprom_am6_get) eeprom parse operation is dynamic.

This removes the option of being able to read the complete eeprom data
in one single shot.

Fortunately, on the I2C bus, we do see the following behavior: In 1
byte mode, if we attempt to read the first header data yet again, the
misbehaving 2 byte addressing device acts in constant addressing mode
which results in the header not matching up and follow on attempt at 2
byte addressing scheme grabs the correct data.

This costs us an extra ~3 milliseconds, which is a minor penalty
compared to the consistent image support we need to have.

Reported-by: Jason Kridner <jkridner@beagleboard.org>
Fixes: a58147c2db ("board: ti: common: board_detect: Do 1byte address checks first.")
Signed-off-by: Nishanth Menon <nm@ti.com>
2022-09-29 10:10:39 -04:00
Andre Przywara
c47bb10a4d vexpress64: also consider DTB pointer in x1
Commit c0fce929564f("vexpress64: fvp: enable OF_CONTROL") added code to
consider a potential DTB address being passed in the x0 register, or
revert to the built-in DTB otherwise.
The former case was used when using the boot-wrapper, to which we sell
U-Boot as a Linux kernel. The latter was meant for TF-A, for which we
couldn't find an easy way to use the DTB it uses itself. We have some
quirk to filter for a valid DTB, as TF-A happens to pass a pointer to
some special devicetree blob in x0 as well.

Now the TF-A case is broken, when enabling proper emulation of secure
memory (-C bp.secure_memory=1). TF-A carves out some memory at the top
of the first DRAM bank for its own purposes, and configures the
TrustZone DRAM controller to make this region secure-only. U-Boot will
then hang when it tries to relocate itself exactly to the end of DRAM.
TF-A announces this by carving out that region of the /memory node, in
the DT it passes on to BL33 in x1, but we miss that so far.

Instead of repeating this carveout in our DT copy, let's try to look for
a DTB at the address x1 points to as well. This will let U-Boot pick up
the DTB provided by TF-A, which has the correct carveout in place,
avoiding the hang.
While we are at it, make the detection more robust: the length test (is
the DT larger than 256 bytes?) is too fragile, in fact the TF-A port for
a new FVP model already exceeds this. So we test x1 first, consider 0
an invalid address, and also require a /memory node to detect a valid DTB.

And for the records:
Some asking around revealed what is really going on with TF-A and that
ominous DTB pointer in x0: TF-A expects EDK-2 as its non-secure payload
(BL33), and there apparently was some long-standing ad-hoc boot protocol
defined just between the two: x0 would carry the MPIDR register value of
the boot CPU, and the hardware DTB address would be stored in x1.
Now the MPIDR of CPU 0 is typically 0, plus bit 31 set, which is defined
as RES1 in the ARMv7 and ARMv8 architectures. This gives 0x80000000,
which is the same value as the address of the beginning of DRAM (2GB).
And coincidentally TF-A put some DTB structure exactly there, for its
own purposes (passing it between stages). So U-Boot was trying to use
this DTB, which requires the quirk to check for its validity.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Peter Hoyes <peter.hoyes@arm.com>
2022-09-29 10:10:39 -04:00
Pankaj Raghav
34d5feaefe fs: btrfs: remove the usage of undeclared fs_mutex variable
This line probably got in by mistake as there is no fs_mutex member in
the btrfs_fs_info struct.

Signed-off-by: Pankaj Raghav <p.raghav@samsung.com>
Reviewed-by: Qu Wenruo <wqu@suse.com>
2022-09-29 10:10:39 -04:00
Michael Trimarchi
dc1c02cb59 configs: rockchip: Drop TPL_MAX_SIZE definition
The max size is defined at architectural level. On the same commit
I have checked mostly all the other architecture and look like they are

Fixes: commit ca8a329a1b ("Convert CONFIG_SPL_PAD_TO et al to Kconfig")
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-09-29 10:10:39 -04:00
Tom Rini
d779fc399c Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- autoboot: make sure watchdog device(s) are handled with keyed
  autoboot (Rasmus)
- gpio_wdt: use __udelay() to avoid recursion (Rasmus)
- watchdog: max6370: use __udelay() to avoid recursion (Pali)
2022-09-27 11:05:37 -04:00
Tom Rini
01c88e3dcd - Increase SYS_MALLOC_F_LEN for STM32 MCU's board
- SPL fixes for STM32F7 MCUs
 - Device tree alignement with kernelv6.0-rc4 for MCU's board
 - Device tree alignement with kernelv6.0-rc3 for MPU's board
 - Update DDR node for STM32MP15
 - Cleanup config file for STM32MP1
 - Update for cmd_stm32key command
 - Fix compatible string to add partitions for STM32MP1
 - Update for stm32programmer tool
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Merge tag 'u-boot-stm32-20220927' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

- Increase SYS_MALLOC_F_LEN for STM32 MCU's board
- SPL fixes for STM32F7 MCUs
- Device tree alignement with kernelv6.0-rc4 for MCU's board
- Device tree alignement with kernelv6.0-rc3 for MPU's board
- Update DDR node for STM32MP15
- Cleanup config file for STM32MP1
- Update for cmd_stm32key command
- Fix compatible string to add partitions for STM32MP1
- Update for stm32programmer tool
2022-09-27 08:53:51 -04:00
Rasmus Villemoes
c11cedc876 autoboot: make sure watchdog device(s) are handled with keyed autoboot
Currently, AUTOBOOT_KEYED and its variant AUTOBOOT_ENCRYPTION are
broken when one has an external always-running watchdog device with a
timeout shorter than the configured boot delay (in my case, I have a
gpio-wdt one with a timeout of 1 second), because we fail to call
WATCHDOG_RESET() in the loops where we wait for the bootdelay to
elapse.

This is done implicitly in the !AUTOBOOT_KEYED case,
i.e. abortboot_single_key(), because that loop contains a
udelay(10000), and udelay() does a WATCHDOG_RESET().

To fix this, simply add similar udelay() calls in the other loops.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-27 12:25:51 +02:00
Pali Rohár
c5f5ee3732 watchdog: max6370: use __udelay() to avoid recursion
The udelay() function in lib/time.c contains a WATCHDOG_RESET()
call. So use __udelay() in max6370_wdt.c to prevent recursion.

Fixes: 0a095fc53b ("watchdog: Add MAX6370 watchdog timer driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-27 12:25:51 +02:00
Rasmus Villemoes
51443c9a49 watchdog: gpio_wdt: use __udelay() to avoid recursion
The udelay() function in lib/time.c contains a WATCHDOG_RESET()
call. The only reason this doesn't lead to a catastrophic infinite
recursion is due to the rate-limiting in wdt-uclass.c:

		if (time_after_eq(now, priv->next_reset)) {
			priv->next_reset = now + priv->reset_period;
			wdt_reset(dev);
		}

But this would fall apart if ->next_reset was updated after calling the
device's reset method.

This is needlessly fragile, and it's easy enough to avoid that
recursion in the first place by just using __udelay() directly.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-27 12:25:40 +02:00
Patrice Chotard
762d410e0d configs: increase SYS_MALLOC_F_LEN for STM32 MCU's board
Some STM32 MCU's board need their SYS_MALLOC_F_LEN value enlarged
to avoid the "alloc space exhausted" error message during their boot
process.
Use the default SYS_MALLOC_F_LEN value which is set to 0x2000 in
Kconfig.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-27 10:41:02 +02:00
Tom Rini
55ccdee315 Xilinx changes for v2023.01-rc1 (round 2)
xilinx:
 - Add support for new Versal NET SOC
 
 zynqmp:
 - Use mdio bus for ethernet phy description
 - Wire ethernet phy reset via i2c-gpio
 
 versal:
 - Config cleanup
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Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.01-rc1 (round 2)

xilinx:
- Add support for new Versal NET SOC

zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio

versal:
- Config cleanup
2022-09-26 11:28:14 -04:00
Tom Rini
ffa2c88bcf Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next 2022-09-26 11:27:30 -04:00
Patrice Chotard
2b5dee9485 configs: stm32f746-disco: Remove CONFIG_SYS_UBOOT_START flag
By pressing "c" key during SPL execution, we force U-boot execution
instead of a kernel XIP image.

This fixes a hard fault when booting stm32f746-disco in SPL with "c"
key pressed during SPL execution.

U-Boot SPL 2022.10-rc5-00009-g40d02baa91 (Sep 20 2022 - 17:21:21 +0200)
Trying to boot from XIP
Hard fault
pc : 080083fc    lr : 08000d1b    xPSR : 21000000
r12 : 2004f108   r3 : 080083fd    r2 : 00000028
r1 : 2004f0c8    r0 : 2004f0e4
Resetting CPU ...

This is due to SYS_UBOOT_START flag set to 0x080083FD which is not correct.
If unset, SYS_UBOOT_START is set by default to CONFIG_SYS_TEXT_BASE
which match with our requirement.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26 17:21:09 +02:00
Patrice Chotard
3cc471d30a configs: stm32f769-disco: Fix internal flash size
arch-stm32f7/stm32.h file is shared between STM32F746 and STM32F769
MCUs. But STM32F769 embeds 2MB of internal flash instead of 1MB for
STM32F746. The flash layout is quite similar between the 2 SoCs :

	STM32F746 			STM32F769
4 *  32KB sectors 			4 *  32KB sectors
1 * 128KB sector 			1 * 128KB sector
3 * 256KB sectors			7 * 256KB sectors

Update sect_sz_kb[] structure and SYS_MAX_FLASH_SECT accordingly.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26 17:21:02 +02:00
Patrice Chotard
ab5c4e5b0f configs: stm32746g-eval: Fix CONFIG_SYS_SPL_ARGS_ADDR
STM32F746 embeds 1 MB of internal flash [0x08000000-0x080fffff],
fix CONFIG_SYS_SPL_ARGS_ADDR accordingly
It solves hard fault when jumping from SPL to U-Boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26 17:03:06 +02:00
Patrice Chotard
4b2bcca5c3 configs: stm32f746-disco: Fix CONFIG_SYS_SPL_ARGS_ADDR
STM32F746 embeds 1 MB of internal flash [0x08000000-0x080fffff],
fix CONFIG_SYS_SPL_ARGS_ADDR accordingly
It solves hard fault when jumping from SPL to U-Boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26 17:03:06 +02:00
Patrice Chotard
4f174e6ffa configs: stm32746g-eval: Fix SPL boot
Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")'
replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR.
As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it
increases SPL size over the initial 0x8000 limit.
Increase the SPL size to 0x9000 to fix SPL boot.
Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future.

Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")'

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26 17:03:06 +02:00
Patrice Chotard
c8b577ce82 configs: stm32f769-disco: Fix SPL boot
Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")'
replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR.
As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it
increases SPL size over the initial 0x8000 limit.
Increase the SPL size to 0x9000 to fix SPL boot.
Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future.

Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")'

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26 17:03:06 +02:00
Patrice Chotard
6ee64732b1 configs: stm32f746-disco: Fix SPL boot
Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")'
replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR.
As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it
increases SPL size over the initial 0x8000 limit.
Increase the SPL size to 0x9000 to fix SPL boot.
Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future.

Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")'

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26 17:03:06 +02:00
Patrice Chotard
9f603e2fff ARM: dts: stm32: DT sync with kernel v6.0-rc4 for MCU's boards
Device tree alignment with kernel v6.0-rc4.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-26 15:19:57 +02:00
Tom Rini
f117c54cc8 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- gpio: turris_omnia_mcu: Fix registering gpios (Pali)
2022-09-26 08:30:17 -04:00
Tom Rini
d9993452cb Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- DWC2 gadget EP fix, nuvoton NPCM7xx ehci/ohci driver
2022-09-26 08:29:42 -04:00
Michal Simek
f2641f066b arm64: versal-net: Add support for mini configuration
Versal NET mini configuration is designed for running memory test. Current
output is on DCC but changing serial0 alias to pl011 will move console to
serial port.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aec3f41a4cc48c45b8f07dd6e423d5838dbcc9d7.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:30 +02:00
Michal Simek
ce40cbdf1f arm64: versal-net: Add defconfig for Versal NET
Use one defconfig for supporting multiple different platforms. DTB
reselection is enabled to choose DT based on SOC detection.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/82cc7c1ca8850270cc2ebc992d835a37aa3d236f.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Jay Buddhabhatti
a41c33992a reset: zynqmp: Enable reset driver for Versal NET
Enable zynqmp reset driver for Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8c26618f87d8451c6ffa9487809a24718bff6a7.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Jay Buddhabhatti
b6b2ad1cea mailbox: zynqmp: Enable ipi mailbox driver for Versal NET
Enable mailbox configs for Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b3a9a6a58b74d17e2ec5f60617fa42062fbab951.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Jay Buddhabhatti
2a00cef820 firmware: zynqmp: Add Versal NET compatible string
Add compatible string for Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ec73f786e1c89094752ff3693f6f0fb4536c85c5.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00
Jay Buddhabhatti
ff33227819 clk: versal: Enable clock driver for Versal NET
Add support for Versal NET compatible string in clock driver.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20a35d0c1ffcc222fbe93dd406cdd0aff92f5223.1663589964.git.michal.simek@amd.com
2022-09-26 14:23:29 +02:00