Merge branch '2022-09-29-assorted-fixes'

- Assorted fixes we want to include before the release.
This commit is contained in:
Tom Rini 2022-09-29 16:06:19 -04:00
commit 97c0a9c570
21 changed files with 41 additions and 26 deletions

View file

@ -7,6 +7,6 @@
save_boot_params:
adr x8, prior_stage_fdt_address
str x0, [x8]
stp x0, x1, [x8]
b save_boot_params_ret

View file

@ -100,7 +100,7 @@ int dram_init_banksize(void)
* Push the variable into the .data section so that it
* does not get cleared later.
*/
unsigned long __section(".data") prior_stage_fdt_address;
unsigned long __section(".data") prior_stage_fdt_address[2];
#ifdef CONFIG_OF_BOARD
@ -151,6 +151,23 @@ static phys_addr_t find_dtb_in_nor_flash(const char *partname)
}
#endif
/*
* Filter for a valid DTB, as TF-A happens to provide a pointer to some
* data structure using the DTB format, which we cannot use.
* The address of the DTB cannot be 0, in fact this is the reserved value
* for x1 in the kernel boot protocol.
* And while the nt_fw_config.dtb used by TF-A is a valid DTB structure, it
* does not contain the typical nodes and properties, which we test for by
* probing for the mandatory /memory node.
*/
static bool is_valid_dtb(uintptr_t dtb_ptr)
{
if (dtb_ptr == 0 || fdt_magic(dtb_ptr) != FDT_MAGIC)
return false;
return fdt_subnode_offset((void *)dtb_ptr, 0, "memory") >= 0;
}
void *board_fdt_blob_setup(int *err)
{
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
@ -172,10 +189,12 @@ void *board_fdt_blob_setup(int *err)
}
#endif
if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC &&
fdt_totalsize(prior_stage_fdt_address) > 0x100) {
if (is_valid_dtb(prior_stage_fdt_address[1])) {
*err = 0;
return (void *)prior_stage_fdt_address;
return (void *)prior_stage_fdt_address[1];
} else if (is_valid_dtb(prior_stage_fdt_address[0])) {
*err = 0;
return (void *)prior_stage_fdt_address[0];
}
if (fdt_magic(gd->fdt_blob) == FDT_MAGIC) {

View file

@ -444,6 +444,16 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
if (rc)
return rc;
/*
* Handle case of bad 2 byte eeproms that responds to 1 byte addressing
* but gets stuck in const addressing when read requests are performed
* on offsets. We re-read the board ID to ensure we have sane data back
*/
rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC,
sizeof(board_id), (uint8_t *)&board_id);
if (rc)
return rc;
if (board_id.header.id != TI_AM6_EEPROM_RECORD_BOARD_ID) {
pr_err("%s: Invalid board ID record!\n", __func__);
return -EINVAL;

View file

@ -452,7 +452,6 @@ static const struct pci_flag_info {
{ PCI_REGION_PREFETCH, "prefetch" },
{ PCI_REGION_SYS_MEMORY, "sysmem" },
{ PCI_REGION_RO, "readonly" },
{ PCI_REGION_IO, "io" },
};
static void pci_show_regions(struct udevice *bus)

View file

@ -150,13 +150,13 @@ static int initr_reloc_global_data(void)
*/
gd->env_addr += gd->reloc_off;
#endif
#ifdef CONFIG_OF_EMBED
/*
* The fdt_blob needs to be moved to new relocation address
* incase of FDT blob is embedded with in image
*/
gd->fdt_blob += gd->reloc_off;
#endif
if (CONFIG_IS_ENABLED(OF_EMBED) && CONFIG_IS_ENABLED(NEEDS_MANUAL_RELOC))
gd->fdt_blob += gd->reloc_off;
#ifdef CONFIG_EFI_LOADER
/*
* On the ARM architecture gd is mapped to a fixed register (r9 or x18).

View file

@ -17,7 +17,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000

View file

@ -19,7 +19,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x40000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000

View file

@ -17,7 +17,6 @@ CONFIG_SPL_STACK_R_ADDR=0x60600000
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x61800800
CONFIG_TPL_MAX_SIZE=0x100000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000

View file

@ -16,7 +16,6 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x40000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000

View file

@ -18,7 +18,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000

View file

@ -18,7 +18,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x40000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000

View file

@ -16,7 +16,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x40000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000

View file

@ -20,7 +20,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000

View file

@ -18,7 +18,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000

View file

@ -18,7 +18,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000

View file

@ -18,7 +18,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000

View file

@ -16,7 +16,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x40000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000

View file

@ -17,7 +17,6 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x40000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000

View file

@ -16,7 +16,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_TPL_MAX_SIZE=0x40000
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000

View file

@ -782,8 +782,6 @@ struct btrfs_fs_info *btrfs_new_fs_info(void)
fs_info->fs_root_tree = RB_ROOT;
cache_tree_init(&fs_info->mapping_tree.cache_tree);
mutex_init(&fs_info->fs_mutex);
return fs_info;
free_all:
btrfs_free_fs_info(fs_info);

5
tools/env/fw_env.c vendored
View file

@ -192,10 +192,13 @@ static int ubi_get_volnum_by_name(int devnum, const char *volname)
&tmp_devnum, &volnum);
if (ret == 2 && devnum == tmp_devnum) {
if (ubi_check_volume_sysfs_name(dirent->d_name,
volname) == 0)
volname) == 0) {
closedir(sysfs_ubi);
return volnum;
}
}
}
closedir(sysfs_ubi);
return -1;
}