Commit graph

32476 commits

Author SHA1 Message Date
Kishon Vijay Abraham I
0a7ab045b9 TI PHY: Add support to control 2nd USB PHY in DRA7xx/AM57xx
Added support to power on/power off the second USB PHY present in
DRA7xx and AM57xx.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:20 -04:00
Kishon Vijay Abraham I
7beaf8b690 ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2
Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:19 -04:00
Kishon Vijay Abraham I
8af1be7678 usb: dwc3: dwc3-omap: Use the clear register inorder to clear the interrupts
Writing "0x00" to the USBOTGSS_IRQENABLE_SET_MISC and
USBOTGSS_IRQENABLE_SET_0 doesn't disable the interrupts. Used
USBOTGSS_IRQENABLE_CLR_MISC and USBOTGSS_IRQENABLE_CLR_0 instead.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:19 -04:00
Andreas Bießmann
2d9efa1227 Makefile: fix SOURCE_DATE_EPOCH for *BSD host
The SOURCE_DATE_EPOCH mechanism for reproducible builds require some date(1)
with -d switch to print the relevant date and time strings of another point of
time.

In other words it requires some date(1) that behaves like the GNU date(1) [1].
The BSD date(1) [2] on the other hand has the same switch but with a different
meaning.

Respect this and check the date(1) abilities before usage, error on non
working version.  Use the well known pre- and suffixes for the GNU variant of
a tool on *BSD hosts to search for a working date(1) version.

[1] http://man7.org/linux/man-pages/man1/date.1.html [2]
http://www.freebsd.org/cgi/man.cgi?query=date

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-28 12:33:19 -04:00
Andreas Bießmann
9316412f46 picosam9g45: adopt CONFIG_SYS_PROMPT
Commit 181bd9dc61 introduced Kconfig selection
for SYS_PROMPT. When applying the new picosam9g45 board this change slipped
through, adopt it.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-28 12:33:18 -04:00
Andreas Bießmann
610751e94f at91sam9260ek: add missing files to MAINTAINERS
This fixes the following genboardscfg.py warnings:

---8<---
WARNING: no status for 'at91sam9g20ek_2mmc'
WARNING: no maintainers for 'at91sam9g20ek_2mmc'
--->8---

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-28 12:33:18 -04:00
Andreas Bießmann
7751604ca9 at91sam9rlek: add missing files to MAINTAINERS
This fixes following genboardscfg.py warning:

---8<---
WARNING: no status for 'at91sam9rlek_mmc'
WARNING: no maintainers for 'at91sam9rlek_mmc'
--->8---

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-28 12:33:18 -04:00
Paul Kocialkowski
8ceb34a1d1 omap-common: SYS_BOOT fallback logic correction and support for more devices
The SYS_BOOT-based fallback shouldn't only check for one of the conditions of
use and then let the switch/case handle each boot device without enforcing the
conditions for each type of boot device again.

For instance, this behaviour would trigger the fallback for UART when
BOOT_DEVICE_UART is defined, CONFIG_SPL_YMODEM_SUPPORT is enabled (which should
be a show-stopper) and e.g. BOOT_DEVICE_USB is enabled and not
CONFIG_SPL_USB_SUPPORT.
Separating the logic for USB and UART solves this.

In addition, this adds support for more peripheral devices (USBETH and CPGMAC)
to the fallback mechanism. Note that the USBETH boot device should always be
different from the USB boot device (each should match a different bootrom
handoff case).

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
2015-08-28 12:33:18 -04:00
Marcel Ziswiler
4519668b29 mtd/nand/ubi: assortment of alignment fixes
Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer
alignment into account which led to failures of the following form:

ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
[trini: Add __UBOOT__ hunk to lib/zlib/zutil.c due to malloc.h in common.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:17 -04:00
Stefan Roese
285e266b41 arm: spear: Some changes / updates to the x600 config header
This patch brings the following changes to the x600 board support:

- Add USB EHCI support
- Add VFAT support for USB key file access
- Increase malloc size (for UBI / UBIFS usage)
- Enable Thumb mode to save some image space
- Remove unreferenced CONFIG_STACKSIZE
- Remove unreferenced CONFIG_SPL_NO_PRINTF

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
2015-08-28 12:33:17 -04:00
Stefan Roese
f49cc22f5c arm: spear: Enable caches on SPEAr
The designware ethernet driver supports d-cache now. So there is nothing
stopping us now to enable the caches completely on SPEAr.

Tested on SPEAr600 x600 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
2015-08-28 12:33:17 -04:00
Stefan Roese
2fbdbda1c7 arm: spear: Move to common SPL infrastructure
The SPL implementation for SPEAr600 is older than the common SPL
infrastructure. This patch now moves the SPEAr600 SPL over to the
common SPL code.

Tested on the only SPEAr board that currently uses SPL in mainline
U-Boot, the x600.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
2015-08-28 12:33:16 -04:00
Stefan Roese
80999a5277 arm: spear: Fix booting - relocate vector table to 0 (low-vector)
Booting SPEAr600 eval board doesn't work with current mainline U-Boot. With
this patch the low-vector bit is left to '0'. Resulting in the common
relocation of the vectors to 0 (SDRAM) to work correctly.

Tested on the SPEAr600 EVB.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
2015-08-28 12:33:16 -04:00
Lokesh Vutla
76b3f195e9 ARM: k2l: Fix device speeds
ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.
Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue

Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection")
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:16 -04:00
Lokesh Vutla
be8ce70c02 ARM: keystone2: Update README
Update README to include uart boot mode support and makefile
changes.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:15 -04:00
Lokesh Vutla
45fe4b4035 ARM: keystone2: Build MLO by default
MLO(NAND/MMC boot image), is used for all the ks2 platforms.
Enabling it in config.mk so that these images will be automatically
built upon calling make. u-boot-spi.gph is already the build target,
so not including here.

Reported-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:15 -04:00
Lokesh Vutla
5f586e9fa1 ARM: keystone2: Rename u-boot-nand.gph to MLO
NAND boot mode, ROM expects an image with a gp header in the
beginning and an 8bytes filled with zeros at the end. The same is
true for SD boot on K2G platforms but the file name should be MLO.

Renaming u-boot-nand.gph to MLO, so that same image can be used for
NAND and SD boots. And also not including all the u-boot only images
under CONFIG_SPL_BUILD.

Reported-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:15 -04:00
Nishanth Menon
cd43ddc019 ARM: keystone2: move the custom build rules out to keystone specific makefile
Keystone has build rules introduced by commit ef509b9063 ("k2hk: add
support for k2hk SOC and EVM") and commit 0e7f2dbac6 ("keystone: add
support for NAND gpheader image").

These are not reused by other platforms for the build, hence there is no
clear benefit is maintaining them in the generic makefile as a build
target. move these to the keystone specific make option

Original idea of using config.mk by Lokesh Vutla <lokeshvutla@ti.com>

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:15 -04:00
Lokesh Vutla
401f2d91ac ARM: keystone2: configs: Move SP to end of u-boot section
Currently u-boot stack is defined at the beginning of MSMC RAM.
This is a problem for uart boot mode as ROM downloads directly to
starting of MSMC RAM.
Fixing it by moving stack to the end of u-boot section and shifting
SYS_TEXT_BASE to the start of MSMC RAM.
Updated division of MSMC RAM is shown below:
	-----------------------------------------
	|		|	|		|
	| U-Boot text	|U-Boot	| SPL text	|
	| download	| Stack	| Download +	|
	|		|	| SPL_BSS +	|
	|		|	| SPL_STACK	|
	-----------------------------------------
	[1]		[2]	[3]		[4]

[1] SYS_TEXT_BASE (Start of MSMC RAM)
[2] SPL_TEXT_BASE - GBL_DATA_SIZE
[3] SPL_TEXT_BASE
[4] END of SPL

[1] + [2] is at least 1M on all platforms, so no chance of overlap.

Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:14 -04:00
Hans de Goede
a85da21f75 env_mmc: Properly prefix mmc errors with '!'
The set_default_env() function from env_common.c expects either
a fully formatted error msg, e.g.: "## Resetting to default environment\n"
or an error msg prefixed with an !, in which case it will format it.

Fix the init_mmc_for_env() error messages to be prefixed with a !
this changes the bootup-log on sunxi when no mmc card is found from:

MMC:   SUNXI SD/MMC: 0
No MMC card foundIn:    serial
Out:   serial

To:

MMC:   SUNXI SD/MMC: 0
*** Warning - No MMC card found, using default environment

In:    serial
Out:   serial

Which clearly is how things should look.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-08-28 12:33:14 -04:00
Simon Glass
972ea53390 malloc_simple: Correct the alignment logic in memalign_simple()
This should use the align parameter, not bytes. Natural alignment is one
use case but should not be the only one supported by this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:14 -04:00
Ulf Magnusson
90c36d8ab9 kconfiglib: update to the latest version
Corresponds to ba71a0e (Fix _parse_block() 'parent' documentation re.
ifs.) from upstream, just adding the SPDX tag.

Has performance improvements, code cleanup, Python 3 support, and various
small fixes, including the following:

  - Unset user values when loading a zero-byte .config. (5e54e2c)
  - Ignore indented .config assignments. (f8a7510)
  - Do not require $srctree to be set for non-kernel projects. (d56e9c1)
  - Report correct locations in the presence of continuation lines.
    (0cebc87)
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
2015-08-28 12:33:13 -04:00
Nishanth Menon
76cff2b108 ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.

Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.

NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:13 -04:00
Nishanth Menon
0358923409 ARM: DRA74-evm: Add iodelay values for SR2.0
Silicon revision 2.0 has new signal routing hence has an updated set of
iodelay parameters to be used. Update the configuration for the same.
Padmux remains the same.

Based on data from VayuES2_EVM_Base_Config-20150807.

NOTE: With respect to the RGMII values, the Manual IODelay values
are used for the fine adjusments needed to meet the tight RGMII
specification.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:13 -04:00
Nishanth Menon
c1ea3bece2 ARM: DRA7: Add detection of ES2.0
Add support for detection of ES2.0 version of DRA7 family of
processors. ES2.0 is an incremental revision with various fixes
including the following:
- reset logic fixes
- few assymetric aging logic fixes
- MMC clock rate fixes
- Ethernet speed fixes
- edma fixes for mcasp

[ravibabu@ti.com: posted internal for an older bootloader]
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:12 -04:00
Chris Packham
70d39f5714 Makefile: Use correct timezone for U_BOOT_TZ
When building with SOURCE_DATE_EPOCH the timezone is in UTC. When
building normally the timezone is taken from the build machine's locale
setting.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-28 12:33:12 -04:00
Suriyan Ramasami
e9015b304a lib/display_options: Fix print_freq
Build without CONFIG_SPL_SERIAL_SUPPORT does not print the cpu freq.
I have seen this in the odroid U3 board, where on boot one sees this:
CPU:   Exynos4412 @  GHz
instead of:
CPU:   Exynos4412 @ 1 GHz

I am assuming that this change was done to get rid of compiler
warnings related to unused variables when building with
CONFIG_SPL_SERIAL_SUPPORT not being defined in an SPL build.

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-28 12:32:36 -04:00
Kun-Hua Huang
b3537c08e1 NDS32: Generic Board Support and Unsupport
Remove ag101 and ag102 support

Signed-off-by: Kun-Hua Huang <kunhua@andestech.com>
2015-08-28 11:46:35 -04:00
Kun-Hua Huang
2e88bb28d8 NDS32: Generic Board Support and Unsupport
Add nds32 ag101p generic board support.

Signed-off-by: Kun-Hua Huang <kunhua@andestech.com>
2015-08-28 11:46:35 -04:00
Jonathan Liu
14006a5671 rpi: set fdt_addr_r to 0x00000100 to match default device_tree_address
Raspberry Pi by default loads the FDT to 0x00000100 so set fdt_addr_r to
match and move scriptaddr to 0x02000000 to avoid clobbering the FDT.

Signed-off-by: Jonathan Liu <net147@gmail.com>
2015-08-28 11:46:35 -04:00
Thierry Reding
9734b97f76 image: Fix loop condition to avoid warning
GCC 5.1 starts warning for comparisons such as !a > 0, assuming that the
negation was meant to apply to the whole expression rather than just the
left operand.

Indeed the comparison in the FIT loadable code is confusingly written,
though it does end up doing the right thing. Rewrite the condition to be
more explicit, that is, iterate over strings until they're exhausted.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-28 11:46:35 -04:00
Tom Rini
79c884d7e4 Merge git://git.denx.de/u-boot-x86 2015-08-26 17:48:05 -04:00
Bin Meng
f4b5db7c53 dm: pci: Document binding of pci device drivers
Document how pci devices are bound to device drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:18 -07:00
Bin Meng
a1f1582b73 x86: crownbay: Support Topcliff integrated pci uart devices with driver model
In order to make a pci uart device node to be properly bound to its
driver, we need make sure its parent node has a compatible string
which matches a driver that scans all of its child device nodes in
the device tree.

Change all pci bridge nodes under root pci node to use "pci-bridge"
compatible driver, as well as corresponding <reg> properties to
indicate its devfn. At last, adding "u-boot,dm-pre-reloc" to each
of these nodes for driver model to initialize them before relocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:17 -07:00
Bin Meng
cdeb2ba99c dm: core: Fix code reentrancy issue in device_probe_child()
The device might have already been probed during the call to
device_probe() on its parent device (e.g. PCI bridge devices).
In its parent device's probe routine, it might probe all of
its child devices via device_probe() thus the codes reenter
device_probe_child(). To support code reentrancy, test these
allocated memory against NULL to avoid memory leak, and return
to the caller if dev->flags has DM_FLAG_ACTIVATED set after
device_probe() returns, so that we don't mess up the device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:17 -07:00
Bin Meng
1887ed3ad6 dm: pci: Optimize pci_uclass_post_bind()
If there is no pci device listed in the device tree,
don't bother scanning the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:17 -07:00
Bin Meng
3242998e24 video: ct69000: Remove unused codes
Remove unused CONFIG_USE_CPCIDVI wrapped codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-08-26 07:54:17 -07:00
Bin Meng
4dd02a752c x86: crownbay: Enable on-board SMSC superio keyboard controller
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.

In order to make PS/2 keyboard work with the VGA console, remove
CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode
using PIRQ routing table, adjust the mask in the device tree to
reserve irq12 which is used by PS/2 mouse.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:16 -07:00
Bin Meng
8ceb2429c9 video: cfb_console: Allow VGA device to work without i8042 keyboard
So far if CONFIG_VGA_AS_SINGLE_DEVICE is not defined, the VGA device
will try to initialize a keyboard device (for x86, it is i8042). But
if i8042 controller initialization fails (eg: there is no keyboard
connected to the PS/2 port), drv_video_init() just simply returns.
This kills the opportunity of using a usb keyboard later with the vga
console, as the vga initialization part is actually ok, only keyboard
part fails. Change the code logic to allow this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-08-26 07:54:16 -07:00
Bin Meng
7d96166b1b x86: i8042: Correctly initialize the controller
The existing i8042 keyboard controller driver has some issues.
First of all, it does not issue a self-test command (0xaa) to the
controller at the very beginning. Without this, the controller
does not respond to any command at all. Secondly, it initializes
the configuration byte register to turn on the keyboard's interrupt,
as U-Boot does not normally allow interrupts to be processed.
Finally, at the end of the initialization routine, it wrongly
sets the controller to disable all interfaces including both
keyboard and mouse.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:16 -07:00
Bin Meng
835dd00050 x86: i8042: Clean up the driver per coding convention
- Rename CamelCase variables to conform U-Boot coding convention
- Rename wait_until_kbd_output_full() to kbd_output_full()
- Change to use macros for i8042 command and control register bits

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:16 -07:00
Bin Meng
3928d66a5e x86: i8042: Reorder static functions
Reorder those static function so that their declarations
can be removed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:15 -07:00
Bin Meng
5e653b0609 x86: i8042: Remove unused codes
Remove unused CONFIG_USE_CPCIDVI wrapped codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:15 -07:00
Simon Glass
df1c9eb505 x86: gpio: Tidy up gpio_ich6_get_base() and callers
This function can return an error. Correct the detection of this error so
that it works even with large 32-bit addresses.

The return value is set up for returning an I/O address but the function is
also used to return a memory-mapped address. Adjust the return code to make
this work.

Also add a bit more debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:15 -07:00
Simon Glass
e7cc0b6f00 x86: gpio: Correct calls to _ich6_gpio_set_direction()
These calls seem to be incorrect. The function expects an I/O address but
the existing callers pass the value at an I/O address. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:15 -07:00
Simon Glass
86645c8932 x86: minnowmax: Correct pad-offset value for host_en1
This should be 0x250, not 0x258. Fix it.

Reported-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:14 -07:00
Simon Glass
dc5740df7e dm: pci: Add a comment to help find pci_hose_read_config_byte, etc.
These functions are defined by macros so do not show up with grep. Add
a comment to help.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:14 -07:00
Simon Glass
cce7e0fa2b x86: minnowmax: Add access to GPIOs E0, E1, E2
These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:14 -07:00
Saket Sinha
bccdf1de75 x86: Add DSDT table for supporting ACPI on QEMU
The DSDT table contains a bytecode that is executed by a driver in the kernel.

Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Tested with QEMU '-M q35'
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:14 -07:00
Saket Sinha
e94019ede7 x86: Add ACPI table support to QEMU
This patch mainly adds ACPI support to QEMU.
Verified by booting Linux kernel on QEMU Q35.

Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Minor whitespace fixes and dropped mention of i440FX in commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:14 -07:00