This patch adds dt-bindings as used by the linux kernel device trees
for the bcm283x family.
Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add i.mx6ul clock header, copied from kernel commit (29b4817d401).
i.MX6ULL reuse the file in Linux Kernel, so let's keep the same.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* Brought in the correct Tegra210 CAR binding; the old file in U-Boot
appears to be a renamed version of the Tegra124 bindings rather than
the real Tegra210 version.
* Conversion of SPI and UART nodes to standard DMA bindings. U-Boot
doesn't use DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
information required by U-Boot, so U-Boot is not affected.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot, including separation of the
Tegra LIC (Legacy IRQ controller) and GIC.
* Node sort order fixes.
Remaining deltas relative to the Linux DT:
* U-Boot has enabled PCIe for Tegra210, but the kernel hasn't yet.
* The GPIO node compatible value in the kernel explicitly includes
Tegra124 values whereas U-Boot does not. I'll send a kernel patch to
correct this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* USB phy_type property is aligned with the kernel, so board files are
updated so the final DT content doesn't change. I'm not convinved that
Nyan uses HSIC phy_type. However, I'd rather this change be a no-op,
and any DT bug-fixes be separate.
* Sync misc changes from the kernel: missing DT content, minor compatible
value fixes, typos.
Remaining deltas relative to the Linux DT:
* U-Boot uses #address-cells/#size-cells of 1 whereas the kernel uses 2.
I believe U-Boot's DT parsing currently assumes that these values match
the physical address size, so I didn't synchronize this part of the DT.
* U-Boot uses the original XUSB PHY DT binding, wherease the kernel DT
has moved to a newer version. Thus, XUSB client nodes include properties
names phys and phy-names that do not appear in the kernel, and don't
include pad definitions in the padctl node.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use
DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
information required by U-Boot, so U-Boot is not affected.
* Boards need to define the clk32k_in clock that feeds the Tegra PMC.
* Addition of tegra114-mc.h since tegra114.dtsi now includes it.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot.
* Node sort order fixes.
Remaining deltas relative to the Linux DT:
* USB node compatible values in U-Boot explicitly list Tegra114 values
whereas the kernel does not. I'll send a kernel patch to correct this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* Modification of PCIe memory region addresses. The HW memory layout is
programmable, so this should work fine, and Beaver PCIe was tested
without issue.
* Removal of pcie_xclk from the PCIe node and clock binding header. This
clock doesn't exist and isn't used; only a reset with this ID exists.
* Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use
DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
information required by U-Boot, so U-Boot is not affected.
* Changed the phy_type value for the second USB port. This required board
DTs to be updated to keep the same configuration.
* Boards need to define the clk32k_in clock that feeds the Tegra PMC.
* Addition of tegra30-mc.h since tegra30.dtsi now includes it.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot.
* Node sort order fixes.
Remaining deltas relative to the Linux DT:
* None.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This brings in a few minor fixes since the last sync. The largest change
is the removal of the definition for TEGRA20_CLK_PCIE_XCLK. This clock
doesn't actually exist.
Remaining deltas:
* Addition of u-boot,dm-pre-reloc property to a couple of nodes.
* Addition of the NAND controller, which Linux doesn't yet support.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This version is based on the Marvell U-Boot version with this patch
applied as latest patch:
Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb
device mode" from 2016-07-05.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Hua Jing <jinghua@marvell.com>
Cc: Terry Zhou <bjzhou@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Import a copy of the dt-bindings/interrupt-controller/mips-gic.h header
from Linux, such that we can use device trees which include it without
modification.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Import DTS files and dt-bindings includes from Linux 4.8-rc1.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sync dts files with the current (Aug 18th 2016) state of Maxime's
linux/sunxi/for-next repo.
Note this commit also updates configs/MSI_Primo81_defconfig,
adding: "# CONFIG_REQUIRE_SERIAL_CONSOLE is not set", this is necessary
because the tablet does not have a reachable uart so the dts sync
drops its serial0 alias.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. These bindings dictate how to represent the BPMP in device tree.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The DT binding for the Tegra186 HSP module apparently wasn't quite final
when I posted initial U-Boot support for it. Add the final DT binding doc
and adapt all code and DT files to match it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These files are from kernel upstream:
"649a371 Add linux-next specific files for 20160616"
with some modification need by U-Boot:
- chosen with stdout-path to uart2.
- add clock-frequency for uart2
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tegra186's HSP module implements doorbells, mailboxes, semaphores, and
shared interrupts. This patch provides a driver for HSP, and hooks it
into the mailbox API. Currently, only doorbells are supported.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tegra186's GPIO controller register layout is significantly different from
previous chips, so add a new driver for it. In fact, there are two
different GPIO controllers in Tegra186 that share a similar register
layout, but very different port mapping. This driver covers both.
The DT binding is already present in the Linux kernel (in linux-next via
the Tegra tree so far).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org> # v1
Signed-off-by: Tom Warren <twarren@nvidia.com>
According to the Tegra TRM, GPIOs are aggregated into /ports/ of 8 GPIOs,
not into /banks/. Fix <dt-bindings/gpio/tegra-gpio.h> to correctly reflect
this naming convention. While this seems like silly churn, it will become
slightly more important once we introduce the GPIO binding for upcoming
Tegra chips. This mirrors an identical commit in the Linux kernel.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These are used by peach_pit and peach_pi. Add them so they can be referenced
in the device tree files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add a clock driver for Exynos7420 SoC. There are about 25 clock controller
blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks
are added in this initial version of the driver.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add the device tree bindings and the accompanying documentation
for the TI DP83867 Giga bit ethernet phy driver.
The original document was from:
[commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel]
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Import the upstream kernel dts into U-Boot. Currently
only serial is supported, but a lot more DT changes are
queued for v4.7.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit syncs the dt-bindings/input/* headers with the kernel (v4.5)
and adds dt-bindings/clock/sun4i-a10-pll2.h, both are necessary for newer
sunxi dts files to build.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.
The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.
Signed-off-by: Tom Rini <trini@konsulko.com>
Since rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases
we need in uboot
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Import various DT files for am4372, an43xx pinctrl and
am437x-gp-evm from Linux Kernel v4.2
Add config file for this board, enable DM, DM_GPIO, DM_SERIAL
and DM_MMC.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.
Signed-off-by: Simon Glass <sjg@chromium.org>
- Import various DT files for DRA7 / DR72x / dra72-evm from Linux Kernel
v4.1
- Add config file for this board, enable DM and DM_GPIO
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.
Signed-off-by: Tom Warren <twarren@nvidia.com>
This also came from Linux - according to this thread it has a GPL v2
license like arch/arm/mach-omap2/mux.h:
http://lists.denx.de/pipermail/u-boot/2015-June/217827.html
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Ingrid Viitanen <ingrid.viitanen@nokia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds dtsi file for Sandbox PMIC.
It fully describes the PMIC by:
- i2c emul node - with a default settings of 16 registers
- 2x buck regulator nodes
- 2x ldo regulator nodes
The default register settings are set with preprocessor macros:
- VAL2REG(min[uV/uA], step[uV/uA], val[uV/uA])
- VAL2OMREG(mode id)
Both defined in file:
- include/dt-bindings/pmic/sandbox_pmic.h
The Voltage ranges of each regulator can be found in:
- include/power/sandbox_pmic.h
The new file is included into:
- sandbox.dts
- test.dts
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on sandbox:
Tested-by: Simon Glass <sjg@chromium.org>
Bring all the sunxi dts files (and update existing ones) from
mripard/sunxi/dt-for-4.1 (which will be merged into upstream master any
day now). This is necessary so that we can move all sunxi boards over to
the driver model.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add standard dt-bindings macros to be used by Intel Quark MRC node.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add the device tree node for the PCIe controller found on Tegra30 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the device tree node for the PCIe controller found on Tegra20 SoCs.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.
Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
