This can conflict with asm/io.h on some archs, and it isn't needed to build
dwc3-generic.c
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
This driver does not use DM, so use log_xxx instead.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
This logs with the device from struct dwc3. Some files also need to include
dm.h so fields in udevice can be accessed.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
This adds a dev argument to some functions so dev_xxx always has a device
to log with. In one instance we must use use a different log function when
we are compiled without DM_USB.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
ep0.c also need to include dm.h so dev_xxx can access udevice fields.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Use `bus` instead of `dev`.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Remove the indirection.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Usually we can get a device from the current core, but some dev_dbg calls
have been converted to debug, since we are called on a cluster.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
This function is never used anywhere, and it also tries to log with a
nonexistant device.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Use the phy's device.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
`phy` doesn't exist; we need to use `x` instead.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Get the device from phy, or pass the phy in.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Without DM_ETH, cpsw_priv.dev is an eth_device. Just use its name instead.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Pass a udevice into a few functions so `dev` is defined.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
There's no dev to log with, so pass the device along with the priv data.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
netdev_xxx evaluates to printf in U-Boot, so there is no extra info
printed. mvpp2 one of only two drivers which use these functions in U-Boot.
Convert these functions to dev_xxx where possible (and to log_xxx where
not).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Remove some prefixes, or get the device from the phy.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
netdev_xxx evaluates to printf in U-Boot, so there is no extra info
printed. mvneta is one of two drivers which use these functions in U-Boot.
Convert these functions to dev_xxx where possible (and to log_xxx where
not).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
No need for indirection here.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
This member was presumably dropped when this driver was converted from
Linux. However, it is still used in log statements during initialization.
This patch adds the member back. In addition, allocation of struct
vf610_nfc has been moved to the callers of vf610_nfc_nand_init. This allows
it to be allocated by DM (if it is being used) and for dev to be
initialized.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
There are too many levels of indirection when calling dev_err. This is an
artifact of the conversion of brcmnand_host.pdev from a struct
platform_device (which has a member `dev` pointing to a struct device) to
struct udevice.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Use mtd_info to get a device to log with.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
dev needs to be gotten from mbox_chan
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
This adds a udevice parameter to get_best_delay and msdc_set_mclk so they
can call dev_err properly.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Get it from spinand->slave->dev. Another option would be to use
spinand_to_mtd(spinand)->dev, but this is what the existing code uses.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
This fixes dev_xxx() not always being called with a device. In
spi_nor_reg_read, a the slave device may not always be available, so we use
bus and cs instead.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
This header is needed so struct udevice can be used in dev_xxx().
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Usually the device is gotten from sunxi_nfc. This is a struct device and
not a struct udevice, but the whole driver seems to be written wihout DM
anyway...
In a few instances, this patch modifies functions to take an nfc to log
with. In once instance we use mtd_info's device since there is no nfc.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Use the device from any mtd already available, or from the active mtd via
pxa3xx_nand_info if one is not.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
The udevice we are working with is called `bus` and not `dev`.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
This converts calls to dev_err to get the device from ti_sci_info where
appropriate.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
We can't use dev_dbg here because we haven't bound to the device yet. Use
log_debug instead.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Another "virtual" clock (in the sense that it isn't configurable). This
could possibly be done as a clock in the device tree, but I think this is a
bit cleaner.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
To test this function, sandbox CPU must set cpu_platdata.timebase_freq on
bind. It also needs to expose a method to set the current cpu. I also make
some most members of cpu_sandbox_ops static.
On the timer side, the device tree property
sandbox,timebase-frequency-fallback controls whether sandbox_timer_probe
falls back to time_timebase_fallback or to SANDBOX_TIMER_RATE.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This function is designed to be used when a timer used to be initialized by
the cpu (e.g. RISC-V timers), but now is initialized by dm_timer_init. In
such a case, the timer may prefer to use the clocks and clock-frequency
properties, but should be able to fall back on using the cpu's
timebase-frequency.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The riscv-timer driver currently serves as a shim for several riscv timer
drivers. This is not too desirable because it bypasses the usual timer
selection via the driver model. There is no easy way to specify an
alternate timing driver, or have the tick rate depend on the cpu's
configured frequency. The timer drivers also do not have device structs,
and so have to rely on storing parameters in gd_t. Lastly, there is no
initialization call, so driver init is done in the same function which
reads the time. This can result in confusing error messages. To a user, it
looks like the driver failed when trying to read the time, whereas it may
have failed while initializing.
This patch removes the shim functionality from the riscv-timer driver, and
has it instead implement the former rdtime.c timer driver. This is because
existing u-boot users who pass in a device tree (e.g. qemu) do not create a
timer device for S-mode u-boot. The existing behavior of creating the
riscv-timer device in the riscv cpu driver must be kept. The actual reading
of the CSRs has been redone in the style of Linux's get_cycles64.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
The usage of regmap API in the SiFive RAM driver is not correct.
The reg address should be obtained via dev_read_addr_index() API.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Fix a typo
%s/interract/interact/
Use Samsung's capitalization of their trademarks
%s/onenand/OneNAND/
%s/Hyperflash/HyperFlash/
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
[trini: Add other Hyperflash cases as noted by Stefan]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support for Microchip PIT64B timer. The timer is 64 bit length and
is used as a free running counter (in continuous mode with highest values
for period registers). The clock feeding the timer would be no more
than 12.5MHz.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
This fixes HWRNG support on Amlogic GXL, GXM, G12A, G12B & SM1
based boards dues to the lack of the core clock in the device tree.
It was reported breaking EFI boot in the Linux EFI stub, because the
EFI_RNG_PROTOCOL didn't check for the RNG device presence before
installing itself.
The Linux amlogic,meson-rng.yaml doesn't mandate the core clock,
this the clock should be ignores if not present.
Nevertheless, the clock should be present and this should be fixed
on the Linux meson-gxl.dtsi & meson-g12-common.dtsi then synced
with U-Boot.
The change has been tested on a Khadas VIM3, which uses the common
meson-g12-common.dtsi like the Odroid-C4 & Odroid-N2 in Scott's
report, along with the RNG cmd.
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reported-by: Scott K Logan <logans@cottsay.net>
Fixes: bc40eb278b ("drivers/rng: add Amlogic hardware RNG driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Scott K Logan <logans@cottsay.net>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The micrel phy driver is already configuring this values from
device tree. So remove the redundant phy configuration call from
this driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
R8A774A1 is part of Renesas RZ/G2 series and not R-Car, reflect the same
for PINCTRL_PFC_R8A774A1 help description
Alongside, sort the PINCTRL_PFC_R8A774A1 config option as per increasing
number of the SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
- Enhance the 'zboot' command to be more like 'bootm' with sub-commands
- The last series of ACPI core changes for programmatic generation of
ACPI tables
- Add all required ACPI tables for ApolloLake and enable ACPIGEN on
Chromebook Coral
- A feature minor enhancements to the 'hob' command
- Intel edison: Support for writing an xFSTK image via binman
Call mmc_of_parse at probe time to fetch all the host properties
from the DT.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The second clock of the IP block (the generic clock), must be explicitly
enabled.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Peng Fan <pengfan@nxp.com>
clk_set_rate will return rate in case of success and zero in case of
error, however it can also return -ev, but it's an ulong function.
To avoid any issues, disregard the return value of this call.
In case this call actually fails, nothing much we can do anyway, but we
can at least try with the previous values (or DT assigned-clocks)
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add new compatibility string for matching sama7g5 product.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Many I2C devices produce roughly the same ACPI data with just things like
the GPIO/interrupt information being different.
This can be handled by a generic driver along with some information in the
device tree.
Add a generic i2c driver for this purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
LX2160A rev2 uses different PCIe controller, so EP mode DT
nodes also need to be fixed up.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CONFIG_DM_SPI_FLASH is only supported now with passing of driver
conversion deadline from non-DM to DM model. Hence, it's safe to remove
non-DM code check from pfe_spi_flash_init.
Also use CONFIG_ENV_SPI_MODE and CONFIG_ENV_SPI_MAX_HZ instead of
reading reading values from DT.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Fix Coverity issue: RESOURCE_LEAK.
leaked_storage: Variable addr going out of scope leaks the storage it
points to.
Fixes: e0152dbed6 ("net: pfe_eth: Use spi_flash_read API to access
flash memory")
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
All the 10G ports that were working in XFI mode were described as
using XGMII (as PHY_INTERFACE_MODE_XFI was not added at the time).
Add the minimal changes required for the FMan code to support XFI.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
PFE DDR addresses are now stored on to a stack varaiable rather
dynamic allocation.
Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
correction in delay implementation before we exit out of tx timeout.
Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The next DPMAC was always verified if it is enabled. In case of
DPMAC@6, the DPMAC@7 is verified. As DPMAC@7 is disabled, DPMAC@6 will
be considered disabled and not detected by uboot.
Signed-off-by: Grigore Popescu <grigore.popescu@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arm64:
- Support for bigger U-Boot images compiled with PIE
microblaze:
- Extend support for LE/BE systems
zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode
zynqmp-r5:
- Fix MPU mapping and defconfig setting.
xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot
cmd:
- pxe: Add fixing for platforms with manual relocation support
clk:
- fixed_rate: Add DM flag to support early boot on r5
fpga:
- zynqmppl: Use only firmware interface and enable SPL build
serial:
- uartlite: Enable for ARM systems and support endians
mmc:
- zynq: Fix indentation
net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64
kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values
bindings:
- Add binding doc for vsc8531
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Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2021.01
arm64:
- Support for bigger U-Boot images compiled with PIE
microblaze:
- Extend support for LE/BE systems
zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode
zynqmp-r5:
- Fix MPU mapping and defconfig setting.
xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot
cmd:
- pxe: Add fixing for platforms with manual relocation support
clk:
- fixed_rate: Add DM flag to support early boot on r5
fpga:
- zynqmppl: Use only firmware interface and enable SPL build
serial:
- uartlite: Enable for ARM systems and support endians
mmc:
- zynq: Fix indentation
net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64
kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values
bindings:
- Add binding doc for vsc8531
The info of fixed-link PHY is described in DT node instead of
getting from MII, so detect the fixed-link PHY DT node first,
if it doesn't exist then probe the MII.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Reworked to fix gazerbeam config]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.
Fixes: 2932c5a802 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Use virtual address to access the MII block registers instead
of physical address.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
As required by PCI Express spec a delay for at least 100ms after
de-asserting PERST# signal is needed before link training is enabled.
Linux kernels prior to 5.8 version do not automatically disable link
training before de-asserting PERST# signal, therefore this requirement is
not fulfilled.
Above requirement is needed for proper detection of some Compex PCIe WiFi
cards. Otherwise Linux kernel cannot detect it.
To allow using those PCIe cards with older Linux kernel versions booted by
U-Boot compiled with U-Boot a37xx pci driver, disable link training in
U-Boot when unloading this pci driver.
Thanks to DM_FLAG_OS_PREPARE flag, U-Boot automatically unload this driver
when booting Linux kernel.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Some of Marvell A3700 boards use mx25u12835f, specifically uDPU
and ESPRESSObin v7.
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
[a.heider: adapt commit message to mainline]
Signed-off-by: Andre Heider <a.heider@gmail.com>
The fdt_fixup_pcie_ls() scans all PCI devices and assumes that all PCI
root devices are layerscape PCIe controllers. Unfortunately, this is not
true for the LS1028A. There is one additional static PCI root complex
(this contains the networking devices) which has nothing to do with the
layerscape PCIe controllers. On recent U-Boot versions this results in
the following panic:
"Synchronous Abort" handler, esr 0x96000044
elr: 000000009602fa04 lr : 000000009602f9f4 (reloc)
elr: 00000000fbd73a04 lr : 00000000fbd739f4
x0 : 0080000002000101 x1 : 0000000000000000
x2 : 00000000fbde9000 x3 : 0000000000000001
x4 : 0000000000000000 x5 : 0000000000000030
x6 : 00000000fbdbd460 x7 : 00000000fbb3d3a0
x8 : 0000000000000002 x9 : 000000000000000c
x10: 00000000ffffffe8 x11: 0000000000000006
x12: 000000000001869f x13: 0000000000000a2c
x14: 00000000fbb3d2cc x15: 00000000ffffffff
x16: 0000000000010000 x17: 0000000000000000
x18: 00000000fbb3fda0 x19: 0000000000000800
x20: 0000000000000000 x21: 00000001f0000000
x22: 0000000000000800 x23: 0000000000000009
x24: 00000000fbdc3c1b x25: 00000000fbdc28e5
x26: 00000000fbdcc008 x27: 00000000fbdc16e2
x28: 000000000f000000 x29: 00000000fbb3d3a0
Code: 394072a1 f94006a0 34000041 5ac00a94 (b8336814)
Resetting CPU ...
This bug already existed in former versions, but the spurious write was
never trapped, because the destination address was a valid address (by
pure luck).
Make sure the PCI root is actually one of the expected PCIe layerscape
controllers by matching its compatible string.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
fixed-rate driver is not different from clk_fixed_factor and it is required
very early in boot that's why setup flag for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
if conditions should match.
Fixes: a18d09ea38 ("fpga: zynqmp: Add secure bitstream loading for ZynqMP")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile
and zynqmp.c to simplify if/endif logic in zynqmp.c.
This change is mostly done to be able to use CONFIG_IS_ENABLED macro and
obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync.
And removing one line from Topic Miami boards which is not needed because
symbol is not enabled via Kconfig.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
flush_cache() arguments are not type casted to take care of 64 bit
systems. Use phys_addr_t to type cast for it to work properly for 32 bit
and 64 bit systems.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
There are compilation warnings showing up when we compile AXI ethernet
driver for 64bit architectures. Fix them, so that it works on both 32
and 64 bit architectures.
DMA descriptors are not taking care of 64bit addresses. To fix it,
change axidma_bd members as below:
next ==> next_desc
reserverd1 ==> next_desc_msb
phys ==> buf_addr
reserverd2 ==> buf_addr_msb
and update next_desc and buf_addr with lower 32 bits of the addresses,
update next_desc_msb and buf_addr_msb with upper 32 bits of the 64bit
addresses.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with
!DM that's why Kconfig it showing it as error:
WARNING: unmet direct dependencies detected for DM_MTD
Depends on [n]: DM [=n]
Selected by [y]:
- NAND_ARASAN [=y] && MTD_RAW_NAND [=y]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This endinness changes are taken from linux uartlite driver.
Reset TX fifo in control register and check TX fifo empty
flag in lower byte of the status register to detect if it
is a little endian system. Based on this check, program the
registers with le32 or be32 through out the driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in
PL and vice versa. That's why change dependencies and do not limit enabling
just for some platforms.
This is follow up patch based on commit 664e16ce99 ("xilinx: kconfig:
Change Kconfig dependencies for Xilinx drivers").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Find out MDIO bus and enable MDIO access to it if this is done via
different GEM controller. Only works across GEM instances.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The most of drivers are using '_' instead of '-' in driver name. That's why
sync up these names to be aligned. It looks quite bad to see both in use.
It is visible via dm tree command.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The GPIO pins used by the SDHCI controller need to be configured to
allow the interface to work.
Signed-off-by: John Robertson <john.robertson@simiatec.com>
The existing driver is not compatible with the Driver Model.
This patch makes the necessary changes while also removing obsolescent
calls/properties as follows:
- fdtdec_* calls replaced with dev_read_* equivalents;
- 'clock-freq-min-max' property replaced by querying the frequency of
the source clock 'base_clk';
- The card detect erratum workaround is applied during probe rather than
overriding get_cd.
The card detect workaround (Microchip ref. DS80000736E, erratum #15) is
not always needed and can be disabled using a vendor specific DT
property.
Signed-off-by: John Robertson <john.robertson@simiatec.com>
In the live tree API ofnode_parse_phandle_with_args, the cell_count
argument must be used when cells_name is NULL.
But this argument is not provided to the live DT function
of_parse_phandle_with_args even it is provided to
fdtdec_parse_phandle_with_args.
This patch adds support of the cells_count parameter in dev_ and
of_node API to allow migration and support of live DT:
- of_parse_phandle_with_args
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix build failure, it used to get this implicitly through common.h
until f7ae49fc4f (common: Drop log.h from common header).
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Heiko Schocher <hs@denx.de>
Somewhere between v2020.04 and v2020.07 the mpc8xxx_spi driver broke,
I'm guessing due to this hunk
@@ -559,6 +560,8 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
if (ret)
return ret;
+ /* combine the requested flags (for IN/OUT) and the descriptor flags */
+ flags |= desc->flags;
ret = _dm_gpio_set_dir_flags(desc, flags);
from commit 695e5fd546 ("gpio: update dir_flags management"). But
the blame is mostly on the driver itself which seems rather confused:
The chip select gpios are requested with GPIOD_ACTIVE_LOW, but then in
each activate/deactivate, dm_gpio_set_dir_flags() is called with
merely GPIOD_IS_OUT, and then the driver call set_value(0) for
activate.
That used to work, but with the above hunk, the ACTIVE_LOW setting
from the request becomes persistent, so the gpio driver ends up being
asked to set the value to 1 in mpc8xxx_spi_cs_activate().
So drop the dm_gpio_set_dir_flags() calls in the activate/deactivate
functions, and use a value of 1 to mean "logically enabled".
Ideally, I think we should also drop the GPIOD_ACTIVE_LOW from the
request and make it up to the list of gpio cs in DT to indicate
whether that CS is enabled when driven low (as is of course usually
the case), but that requires changing
arch/powerpc/dts/gdsys/gazerbeam-base.dtsi among others, and I don't
have that hardware to test on. I have, however, tested our
own (mpc8309-based) hardware with this change, and I have also tested
that removing the GPIOD_ACTIVE_LOW from the request and updating our
DT as
- gpios = <&spisel 0 0>;
+ gpios = <&spisel 0 GPIO_ACTIVE_LOW>;
still works.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Add master clock (MCK1..MCK4) support for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Add sckc driver compatible with common clock framework. Driver
implements slow clock support for SAM9X60 compatible IPs (in this
list it is also present SAMA7G5's slow clock IP).
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Move clock code to compat.c to allow switching to CCF
without mixing CCF code with non CCF code. This prepares the
field for next commits.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Add helper for clock drivers. These will be used by following
commits in the process of switching AT91 clock drivers to CCF.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
clk_get_by_indexed_prop() retrieves a clock with dev member being set
with the pointer to the udevice for the clock controller driver. But
in case of CCF each clock driver has set in dev member the reference
to its parent (the root of the clock tree is a fixed clock, every
node in clock tree is a clock registered with clk_register()). In this
case the subsequent operations like dev_get_clk_ptr() on clocks
retrieved by clk_get_by_indexed_prop() will fail. For this, get the
pointer to the proper clock registered (with clk_register()) using
clk_get_by_id() before proceeding.
Fixes: 1d7993d1d0 ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Clock re-parenting is not binding the clock's device to its new
parent device, it only calls the clock's ops->set_parent() API. The
changes in this commit re-parent the clock device to its new parent
so that subsequent operations like clk_get_parent() to point to the
proper parent.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In common clock framework the relation b/w parent and child clocks is
determined based on the udevice parent/child information. A clock
parent could be changed based on devices needs. In case this is happen
the functionalities for clock who's parent is changed are broken. Add
a function that reparent a device. This will be used in clk-uclass.c
to reparent a clock device.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The following bugs are fixed:
* incorrect online help for setenv and env
* description of function efi_mem_carve_out()
* replace printf() by log_err() in stm32mp1_rng driver
A unit test is provided to check that the boot hart id is provided in the
RISC-V device-tree.
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Merge tag 'efi-2020-10-rc5-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc5 (2)
The following bugs are fixed:
* incorrect online help for setenv and env
* description of function efi_mem_carve_out()
* replace printf() by log_err() in stm32mp1_rng driver
A unit test is provided to check that the boot hart id is provided in the
RISC-V device-tree.
The logging system provides flexible filtering and enhanced output.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Lot of Qualcomm SoC-s use DWC3 controller for both USB2.0 and USB3.0
ports.
Qualcomm has some custom config registers on top of the generic ones,
but for host mode these are not needed.
So lets add the neccessary compatible string.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs.
The driver sets up HS and SS phys.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
There is already existing driver for SMEM so lets enable it for IPQ40xx as well.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
add DM/DTS support for the UEC ethernet on QUICC Engine
Block.
Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com>
Series-changes: 3
- revert:
commit "3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled")
as now qe works with DM and DM_ETH support.
- fix mailaddress from Holger
Series-changes: 2
- add comments from Qiang Zhao:
- add device node documentation
- I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c
because using drivers/net/fsl_mdio.c leads in none existent
udevice mdio@3320
instead boards with DM ETH support should use now this
driver.
- remove RFC tag
Commit-notes:
- I let the old none DM based implementation in code
so boards should work with old implementation.
This Code should be removed if all boards are converted
to DM/DTS.
- add the DM based qe uec driver under drivers/net/qe
- Therefore copied the files uccf.c uccf.h uec.h from
drivers/qe. So there are a lot of Codingstyle problems
currently. I fix them in next version if this RFC
patch is OK or it needs some changes.
- The dm based driver code is now under drivers/net/qe/dm_qe_uec.c
Used a lot of functions from drivers/qe/uec.c
- seperated the PHY specific code into seperate file
drivers/net/qe/dm_qe_uec_phy.c
END
add DM support for parallel I/O ports on QUICC Engine Block
Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Series-changes: 2
- remove RFC
- fixed Codingstyle errors, therefore new patch
powerpc, mpc83xx: fix codingstyle issues for qe_io.c
- moved DM part to drivers/pinctrl
Commit-notes:
Open questions / discussion:
- I let the old none DM based implementation in code
so boards should work with old implementation.
This should be removed if all boards are converted to
DM/DTS.
- Unfortunately linux DTS does not use "pinctrl-"
properties, instead "pio-handle" properties.
Even worser old U-Boot code initializes all pins
defined in "const qe_iop_conf_t qe_iop_conf_tab[]"
table in board code. As linux does the same I decided
to also scan through all subnodes containing "pio-map"
property and initialize them too.
The proper solution would be to check for "pio-handle"
when a device is probed.
END
- Hyperflash boot for J7200
- Update Main R5FSS lockstep mode
- R5F remoteproc support for J7200
- Minor env fixes
- Add SPI boot support for am335x-icev2
Add an ofdata_to_platdata() callback to access dts in U-boot and
access all platform data in it. This prepares the driver for supporting
both device tree as well as static platform data structures in SPL.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
There are devices which don't use OF_CONTROL or OF_PLATDATA but instead
rely on statically defined platdata. Block dm_scan_fdt_dev() with both
configs to avoid build failures under this condition.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The K3 J7200 SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The integration of
these clusters is very much similar to J721E SoCs otherwise.
The revised IP has the following two new features:
1. TCMs are auto-initialized during module power-up, and the behavior
is programmable through a MMR bit controlled by System Firmware.
2. The LockStep-mode allows the Core1 TCMs to be combined with the
Core0 TCMs effectively doubling the amount of TCMs available.
The LockStep-mode on previous SoCs could only use the Core0 TCMs.
This combined TCMs appear contiguous at the respective Core0 TCM
addresses.
Add the support to these clusters in the K3 R5F remoteproc driver
using J7200 specific compatibles and revised logic accounting for
the above IP features/differences.
Signed-off-by: Suman Anna <s-anna@ti.com>
Use mmc_of_parse() to set the common host properties. That includes
"bus-width", so parsing it can be removed from the driver.
But more importantly, "non-removable" is now respected, which fixes
the usage of eMMC.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Tested-by: Marek Behún <marek.behun@nic.cz>
Since the introduction of 'get_cd' callback in sdhci core,
dragonboard410c's MMC interface is broken. It turns out that 'get_cd'
callback checks for the host_caps for validating the chip select. And
since the msm_sdhci driver is not parsing the host_caps from DT, not
all of the cababilities are parsed properly. This results in the MMC
interfaces to be broken.
Hence, fix this by adding a call to 'mmc_of_parse' during driver probe.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Aníbal Limón <anibal.limon@linaro.org>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Nand writes should skip the bad blocks with "nand write" command.
In case of bad blocks with above 32-bit address, nand_block_isbad()
returns false due to truncated bad block address.
In below code segment,
if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1)))
offset is 64-bit and mtd->erasesize is 32-bit, hence the truncation is
happening. Cast 'mtd->erasesize' with loff_t to fix this issue.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
On the mt7623 platform, if one port enable fail and other port
enable succeed. It will hang on when using pci enum
because the resource was not released correctly.
Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
On the mt7623 platform, if one port enable fail and other port
enable succeed. It will hang on when using pci enum
because the resource was not released correctly.
Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
v2: modify title description aspeed:clock -> clock:aspeed
Use kernel include/dt-bindings/clock/aspeed-clock.h define
for clock driver.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Rename the ast2500-scu.h to aspeed-clock.h.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
The commit 57805f2270 ("net: bcmgenet: Don't set ID_MODE_DIS when
not using RGMII") needed to be extended for the case of using the
rgmii-rxid. The latest version of the Rasbperry Pi4 dtb files for the
5.4 now specify the rgmii-rxid.
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Tested-by: Petr Tesarik <ptesarik@suse.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
This commit fixes a serious issue occurring when several network
commands are run on a raspberry pi 4 board: for instance a "dhcp"
command and then one or several "tftp" commands. In this case,
packet recv callbacks were called several times on the same packets,
and send function was failing most of the time.
note: if the boot procedure is made of a single network
command, the issue is not visible.
The issue is related to management of the packet ring buffers
(producer / consumer) and DMA.
Each time a packet is received, the ethernet device stores it
in the buffer and increments an index called RDMA_PROD_INDEX.
Each time the driver outputs a received packet, it increments
another index called RDMA_CONS_INDEX.
Between each pair of network commands, as part of the driver
'start' function, previous code tried to reset both RDMA_CONS_INDEX
and RDMA_PROD_INDEX to 0. But RDMA_PROD_INDEX cannot be written from
driver side, thus its value was actually not updated, and only
RDMA_CONS_INDEX was reset to 0. This was resulting in a major
synchronization issue between the driver and the device. Most
visible behavior was that the driver seemed to receive again the
packets from the previous commands (e.g. DHCP response packets
"received" again when performing the first TFTP command).
This fix consists in setting RDMA_CONS_INDEX to the same
value as RDMA_PROD_INDEX, when resetting the driver.
The same kind of fix was needed on the TX side, and a few variables
had to be reset accordingly (c_index, tx_index, rx_index).
The rx_index and tx_index have only 256 entries so the bottom 8 bits
must be masked off.
Originated-by: Etienne Dublé <etienne.duble@imag.fr>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Tested-by: Petr Tesarik <ptesarik@suse.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
As the error message is now displayed by generic phy functions,
the dev_err/pr_err can be change to dev_dbg/pr_debug.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
As the error message is now displayed by generic phy functions,
the pr_err can be change to pr_debug.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
As the error message is now displayed by generic phy functions,
the pr_err can be change to pr_debug.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
As the error message is now displayed by generic phy functions,
the dev_err can be change to dev_dbg.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
