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reset: Add IPQ40xx reset controller driver

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On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Robert Marko 2020-09-10 16:00:02 +02:00 committed by Tom Rini
parent 6ef099b29e
commit 8ef7df5df3
5 changed files with 276 additions and 0 deletions
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2
MAINTAINERS
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@ -238,6 +238,8 @@ M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained
F: arch/arm/mach-ipq40xx/
F: include/dt-bindings/clock/qcom,ipq4019-gcc.h
F: include/dt-bindings/reset/qcom,ipq4019-reset.h
F: drivers/reset/reset-ipq4019.c
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>

8
drivers/reset/Kconfig
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@ -148,6 +148,14 @@ config RESET_IMX7
help
Support for reset controller on i.MX7/8 SoCs.
config RESET_IPQ419
bool "Reset driver for Qualcomm IPQ40xx SoCs"
depends on DM_RESET && ARCH_IPQ40XX
default y
help
Support for reset controller on Qualcomm
IPQ40xx SoCs.
config RESET_SIFIVE
bool "Reset Driver for SiFive SoC's"
depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540

1
drivers/reset/Makefile
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@ -23,6 +23,7 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o
obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o

173
drivers/reset/reset-ipq4019.c Normal file
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@ -0,0 +1,173 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Sartura Ltd.
*
* Author: Robert Marko <robert.marko@sartura.hr>
*
* Based on Linux driver
*/
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <dt-bindings/reset/qcom,ipq4019-reset.h>
#include <reset-uclass.h>
#include <linux/bitops.h>
#include <malloc.h>
struct ipq4019_reset_priv {
phys_addr_t base;
};
struct qcom_reset_map {
unsigned int reg;
u8 bit;
};
static const struct qcom_reset_map gcc_ipq4019_resets[] = {
[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
[PCIE_AHB_ARES] = { 0x1d010, 10 },
[PCIE_PWR_ARES] = { 0x1d010, 9 },
[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
[PCIE_PHY_ARES] = { 0x1d010, 6 },
[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
[PCIE_PIPE_ARES] = { 0x1d010, 2 },
[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
[ESS_RESET] = { 0x12008, 0},
[GCC_BLSP1_BCR] = {0x01000, 0},
[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
[GCC_BIMC_BCR] = {0x04000, 0},
[GCC_TLMM_BCR] = {0x05000, 0},
[GCC_IMEM_BCR] = {0x0E000, 0},
[GCC_ESS_BCR] = {0x12008, 0},
[GCC_PRNG_BCR] = {0x13000, 0},
[GCC_BOOT_ROM_BCR] = {0x13008, 0},
[GCC_CRYPTO_BCR] = {0x16000, 0},
[GCC_SDCC1_BCR] = {0x18000, 0},
[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
[GCC_AUDIO_BCR] = {0x1B008, 0},
[GCC_QPIC_BCR] = {0x1C000, 0},
[GCC_PCIE_BCR] = {0x1D000, 0},
[GCC_USB2_BCR] = {0x1E008, 0},
[GCC_USB2_PHY_BCR] = {0x1E018, 0},
[GCC_USB3_BCR] = {0x1E024, 0},
[GCC_USB3_PHY_BCR] = {0x1E034, 0},
[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
[GCC_PCNOC_BCR] = {0x2102C, 0},
[GCC_DCD_BCR] = {0x21038, 0},
[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
};
static int ipq4019_reset_assert(struct reset_ctl *rst)
{
struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
const struct qcom_reset_map *map;
u32 value;
map = &reset_map[rst->id];
value = readl(priv->base + map->reg);
value |= BIT(map->bit);
writel(value, priv->base + map->reg);
return 0;
}
static int ipq4019_reset_deassert(struct reset_ctl *rst)
{
struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
const struct qcom_reset_map *map;
u32 value;
map = &reset_map[rst->id];
value = readl(priv->base + map->reg);
value &= ~BIT(map->bit);
writel(value, priv->base + map->reg);
return 0;
}
static int ipq4019_reset_free(struct reset_ctl *rst)
{
return 0;
}
static int ipq4019_reset_request(struct reset_ctl *rst)
{
return 0;
}
static const struct reset_ops ipq4019_reset_ops = {
.request = ipq4019_reset_request,
.rfree = ipq4019_reset_free,
.rst_assert = ipq4019_reset_assert,
.rst_deassert = ipq4019_reset_deassert,
};
static const struct udevice_id ipq4019_reset_ids[] = {
{ .compatible = "qcom,gcc-reset-ipq4019" },
{ }
};
static int ipq4019_reset_probe(struct udevice *dev)
{
struct ipq4019_reset_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
return 0;
}
U_BOOT_DRIVER(ipq4019_reset) = {
.name = "ipq4019_reset",
.id = UCLASS_RESET,
.of_match = ipq4019_reset_ids,
.ops = &ipq4019_reset_ops,
.probe = ipq4019_reset_probe,
.priv_auto_alloc_size = sizeof(struct ipq4019_reset_priv),
};

92
include/dt-bindings/reset/qcom,ipq4019-reset.h Normal file
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@ -0,0 +1,92 @@
/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef __QCOM_RESET_IPQ4019_H__
#define __QCOM_RESET_IPQ4019_H__
#define WIFI0_CPU_INIT_RESET 0
#define WIFI0_RADIO_SRIF_RESET 1
#define WIFI0_RADIO_WARM_RESET 2
#define WIFI0_RADIO_COLD_RESET 3
#define WIFI0_CORE_WARM_RESET 4
#define WIFI0_CORE_COLD_RESET 5
#define WIFI1_CPU_INIT_RESET 6
#define WIFI1_RADIO_SRIF_RESET 7
#define WIFI1_RADIO_WARM_RESET 8
#define WIFI1_RADIO_COLD_RESET 9
#define WIFI1_CORE_WARM_RESET 10
#define WIFI1_CORE_COLD_RESET 11
#define USB3_UNIPHY_PHY_ARES 12
#define USB3_HSPHY_POR_ARES 13
#define USB3_HSPHY_S_ARES 14
#define USB2_HSPHY_POR_ARES 15
#define USB2_HSPHY_S_ARES 16
#define PCIE_PHY_AHB_ARES 17
#define PCIE_AHB_ARES 18
#define PCIE_PWR_ARES 19
#define PCIE_PIPE_STICKY_ARES 20
#define PCIE_AXI_M_STICKY_ARES 21
#define PCIE_PHY_ARES 22
#define PCIE_PARF_XPU_ARES 23
#define PCIE_AXI_S_XPU_ARES 24
#define PCIE_AXI_M_VMIDMT_ARES 25
#define PCIE_PIPE_ARES 26
#define PCIE_AXI_S_ARES 27
#define PCIE_AXI_M_ARES 28
#define ESS_RESET 29
#define GCC_BLSP1_BCR 30
#define GCC_BLSP1_QUP1_BCR 31
#define GCC_BLSP1_UART1_BCR 32
#define GCC_BLSP1_QUP2_BCR 33
#define GCC_BLSP1_UART2_BCR 34
#define GCC_BIMC_BCR 35
#define GCC_TLMM_BCR 36
#define GCC_IMEM_BCR 37
#define GCC_ESS_BCR 38
#define GCC_PRNG_BCR 39
#define GCC_BOOT_ROM_BCR 40
#define GCC_CRYPTO_BCR 41
#define GCC_SDCC1_BCR 42
#define GCC_SEC_CTRL_BCR 43
#define GCC_AUDIO_BCR 44
#define GCC_QPIC_BCR 45
#define GCC_PCIE_BCR 46
#define GCC_USB2_BCR 47
#define GCC_USB2_PHY_BCR 48
#define GCC_USB3_BCR 49
#define GCC_USB3_PHY_BCR 50
#define GCC_SYSTEM_NOC_BCR 51
#define GCC_PCNOC_BCR 52
#define GCC_DCD_BCR 53
#define GCC_SNOC_BUS_TIMEOUT0_BCR 54
#define GCC_SNOC_BUS_TIMEOUT1_BCR 55
#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
#define GCC_SNOC_BUS_TIMEOUT3_BCR 57
#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
#define GCC_TCSR_BCR 68
#define GCC_QDSS_BCR 69
#define GCC_MPM_BCR 70
#define GCC_SPDM_BCR 71
#endif