Commit graph

68830 commits

Author SHA1 Message Date
Naoki Hayama
047f6ec0b7 README: Convert HTTP links to HTTPS
Convert all the other http:// links to https:// .
www.denx.de/twiki/ seems to move to www.denx.de/wiki/ ,
so change it.

I checked all links in this patch are valid.

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:54 -04:00
Naoki Hayama
81a05d9bcc README: vxworks: Fix typo overwride
%s/overwride/override/

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:53 -04:00
Naoki Hayama
bbb140ed38 README: sandbox: Change reference to sandbox details
doc/arch/index.rst is a list of links to each architecture.
As for the sandbox details, doc/arch/sandbox.rst looks better.

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Naoki Hayama
e4eb313af0 README: Update directory hierarchy
Removed:
- /arch/openrisc

Added:
- /arch/xtensa
- /env

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:53 -04:00
Naoki Hayama
c4bd51e2ae README: Update source code location
This patch include these updates

- Git repository has moved to GitLab
- HTTPS access to the file server is allowed
- pre-built images are no longer available

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:53 -04:00
Naoki Hayama
6681bbb5e9 README: Update links to mailing list archives
This patch includes these updates

- Change http://lists.denx.de/pipermail/u-boot
  to https://lists.denx.de/pipermail/u-boot
- http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
  is broken, so remove it
- Another archive https://marc.info/?l=u-boot
  is available, so add it

Additional information:
dir.gmane.org has moved to news.gmane.io, but it only allows
access to the archive via NNTP.

- Server: news.gmane.io
- Group : gmane.comp.boot-loaders.u-boot

I don't include this information in this patch because
it's not very useful without web interfaces.

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-22 09:54:53 -04:00
Sean Anderson
8af7bb914f timer: Return count from timer_ops.get_count
No timer drivers return an error from get_count. Instead of possibly
returning an error, just return the count directly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Sean Anderson
aff60aba6c doc: Document timer API
This adds kerneldocs for <timer.h>.

I don't know who should maintain doc/api/timer.rst, since the timer
subsystem seems to be maintained by SoC maintainers. MAINTAINERS is left
un-updated for the moment.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Heinrich Schuchardt
c670aeee3d common: rename getc() to getchar()
The sandbox is built with the SDL2 library with invokes the X11 library
which in turn calls getc(). But getc() in glibc is defined as

    int getc(FILE *)

This does not match our definition.

    int getc(void)

The sandbox crashes when called with parameter -l.

Rename our library symbol getc() to getchar().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Rasmus Villemoes
8d5d97cb28 cli_hush.c: remove broken sanity check
This code is intended do prevent one from setting a shell variable abc
by doing

  abc=123

if an environment variable named abc already exists. However, the
check is broken, since the env_get is done before the split on =, so
we look up whether an environment variable "abc=123" exists, which is
obviously never the case.

One could move the code to below the split on =, but instead, just
remove it, saving a little .text: The check has never worked as
intended (it goes all the way back to the initial git commit), and it
would anyway not guard against one first setting the shell variable,
then doing 'env set abc xyz'.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-10-22 09:54:53 -04:00
Heiko Schocher
6ebe6b387f common, autoboot: sync functionality with Kconfig description
add back again special case: -2
autoboot with no delay and no check for abort

as described in Kconfig option, see common/Kconfig
help text for option BOOTDELAY.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Naoki Hayama
898a084953 cosmetic: image: Fix comments and the order of definitions
Fix some comments about functions.
Move genimg_get_comp_name() above genimg_get_short_name() because
genimg_get_comp_name() is related to get_table_entry_name().

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Naoki Hayama
ad5fb9f2e6 mkimage: Skip adding non-existent IDs to a list
In show_valid_options(), this patch introduces checking whether
a category has an entry ID. If not, adding it to a list for output
is skipped before calling qsort().
This patch will affect all kinds of image header categories
(-A, -C, -O and -T flags).

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Naoki Hayama
02d41b01bd image: Add a function to modify category information
Add a generic function which can check whether a category has an
entry ID.

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Ovidiu Panait
2dfdd0c4de Kconfig: Use hex values for CONFIG_{SPL,TPL}_SIZE_LIMIT
CONFIG_{SPL,TPL}_SIZE_LIMIT are defined as hex (SPL_SIZE_LIMIT was
converted in b51882d0 ("spl: Convert CONFIG_SPL_SIZE_LIMIT to hex"), but
there are still places that reference integer values. Change those to hex
as well. Also, update the Makefile to check for 0x0 instead of 0.

This also fixes the following build error when CONFIG_SPL_SIZE_LIMIT
is set by menuconfig to 0x0:
...
spl/u-boot-spl.bin exceeds file size limit:
  limit:  0 bytes
  actual: 0x80f0 bytes
  excess: 0x80f0 bytes

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Simon Glass
39565cc2a9 tpm: cr50: Correct logging statements
Fix up some logging statements in this file. Most of them should use
log_debug(), apart from one error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Simon Glass
acdd248bf2 i2c: designware: Use log_debug() for debugging
We don't want the debug output to be visible in a normal boot. Silence it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
2020-10-22 09:54:52 -04:00
Simon Glass
5630d2fbc5 board: Show memory for frame buffers
When debugging is enabled, show the memory allocated to video frame
buffers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:52 -04:00
Simon Glass
4a08fae196 bloblist: Place on a 4KB boundary
It is much easier to read the bloblist addresses if it starts on a 4KB
boundary. Update it to align it accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:53:31 -04:00
Simon Glass
28dc20f34a syscon: Drop the logging in syscon_get_by_driver_data()
This function can be called when it is not known whether it will find
anything. This results in confusing log messages if the device is not
found. It is better for the caller to log the failure, if necessary.

Drop the logging from this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:53:31 -04:00
Simon Glass
8021296a71 log: Add missing category names
Add some category names that were missed in recent changes. Update the
comment as a reminder.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:53:31 -04:00
Tom Rini
b90daf2743 - Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig
- Fix stm32prog command: parsing of FlashLayout without partition
 - Update MAINTAINERS for ARM STM STM32MP
 - Manage eth1addr on dh board with KS8851
 - Limit size of cacheable DDR in pre-reloc stage in stm32mp1
 - Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
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Merge tag 'u-boot-stm32-20201021' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig
- Fix stm32prog command: parsing of FlashLayout without partition
- Update MAINTAINERS for ARM STM STM32MP
- Manage eth1addr on dh board with KS8851
- Limit size of cacheable DDR in pre-reloc stage in stm32mp1
- Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
2020-10-22 08:25:41 -04:00
Tom Rini
281d94b986 Merge branch '2021.01-rc' of https://github.com/lftan/u-boot
- fix Gen5 enable of EMAC via FPGA
2020-10-22 08:25:14 -04:00
Tom Rini
5d92dacbbe Pull request for UEFI sub-system for efi-2021-01-rc1 (2)
A use after free in the UEFI network stack is fixed.
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Merge tag 'efi-2021-01-rc1-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2021-01-rc1 (2)

A use after free in the UEFI network stack is fixed.
2020-10-21 19:13:05 -04:00
Marek Vasut
5675ed7cb6 Revert "Fix data abort caused by mis-aligning FIT data"
This reverts commit eb39d8ba5f.
The commit breaks booting of fitImage by SPL, the system simply hangs.
This is because on arm32, the fitImage and all of its content can be
aligned to 4 bytes and U-Boot expects just that.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Reuben Dowle <reuben.dowle@4rf.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marex@denx.de>
2020-10-21 19:11:50 -04:00
Patrick Delaunay
53de79fecc stm32mp: stm32prog: accept device without partition
When partitions are not available on a device the command stm32prog raises
an error but a device can have no partition to check in init_device()
and the command need to continue to the next part_id.

This patch correct an issue for ram0 target, when block_dev and mtd
are NULL.

For example with the simple flashlayout file:

Opt	Part	Name	Type	Device	Offset	Binary
-	0x01	fsbl	Binary	none	0x0	tf-a-serialboot.stm32
-	0x03	ssbl	Binary	none	0x0	u-boot.stm32
P	0x10	kernel	System	ram0	0xC2000000	uImage.bin
P	0x11	dtb	FileSytem	ram0	0xC4000000	stm32mp157f-ev1.dtb

Fixes: ffc405e63b ("stm32mp: stm32prog: add upport of partial update")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
33f5000ee8 configs: stm32mp15: activate CMD_ELF
Activate CONFIG_CMD_ELF to accept the command "bootelf".

This patch simplifies the file stm32mp defconfig, as we have
no reason to deactivate this command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
d931186312 configs: stm32mp15: activate CMD_EXPORTENV
Activate CONFIG_CMD_EXPORTENV to accept the command "env export".

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
fba7b95085 configs: stm32mp15: activate CMD_IMPORTENV
Activate CONFIG_CMD_IMPORTENV to accept the command "env import".
This command is useful in script to include some variable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
2bf692d317 MAINTAINERS: Add STM32MP1 RNG driver in stm32mp platform
Add the STM32MP1 RNG driver in the list of drivers supported by
the STMicroelectronics STM32MP15x series.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
ce52023050 MAINTAINERS: Add stm32 and stm regexp for ARM STM STM32MP platform
Add files and directories regex "stm32" and "stm" in "ARM STM STM32MP"
platform to avoid missing files or drivers supported by the
STMicroelectronics series STM32MP15x.

This patch adds the rules already used in Linux kernel for
ARM/STM32 ARCHITECTURE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
6af78d03d3 arm: stm32: cleanup arch gpio.h
Cosmetic update of gpio.h:
- remove enumerate: stm32_gpio_port, stm32_gpio_pin
  because STM32_GPIO_XXX values are unused
- move STM32_GPIOS_PER_BANK in stm32_gpio.c
  as its value is IP dependent and not arch dependent

No functional change as number of banks and number of gpio by banks
is managed by device tree since since DM migration and
commit 8f651ca60b ("pinctrl: stm32: Add get_pins_count() ops").

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Marek Vasut
e07f76b25d ARM: dts: stm32: Do not set eth1addr if KS8851 has EEPROM
In case the KS8851 has external EEPROM attached to it, do not set
eth1addr at all. The network stack will read the MAC out of the
KS8851 and set eth1addr accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
67f9f11f19 stm32mp: limit size of cacheable DDR in pre-reloc stage
In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.

This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.

Without security, in basic boot, the value is equal to STM32_DDR_SIZE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Alexandru Gagniuc
c981d67a04 mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilities
mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of
struct mmc_config from devicetree.
The same logic is duplicated in stm32_sdmmc2_probe(). Use
mmc_of_parse(), which is more generic.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-21 18:11:56 +02:00
Alexandru Gagniuc
f80b8ac69b mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"
"cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no
additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed"
is used for MMC HS at both 26MHz and 52MHz.

Use the same approach and enable MMC_CAP(MMC_HS_52) host capability
when "cap-mmc-highspeed" is found in the devicetree. In the event an
MMC card doesn't support 52 MHz, it will be clocked at a speed based
on its EXT CSD, even on 52 MHz host controllers

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 09:57:14 +02:00
Ralph Siemsen
b0b08ce0b7 arm: socfpga: fix Gen5 enable of EMAC via FPGA
An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.

The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.

Fixes: db5741f7a8 ("arm: socfpga: Convert system manager from struct to defines")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-21 11:45:54 +08:00
Tom Rini
adc0c39633 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- Assorted R-Car Gen3 updates
2020-10-20 08:02:53 -04:00
Tom Rini
f216259927 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- MediaTek USB host support
2020-10-20 08:01:46 -04:00
Lad Prabhakar
b2d7a163ab pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.9
Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Lad Prabhakar
a3c1fd6393 clk: renesas: Import R8A774C0 clock tables from Linux 5.9
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Biju Das
e9d91b82fe clk: renesas: Add R8A774E1 clock tables
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Biju Das
54db9e8b8f clk: renesas: Add R8A774B1 clock tables
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Lad Prabhakar
fc5e552209 arm: dts: r8a774c0: Import DTS from Linux 5.9
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Lad Prabhakar
051f1499c9 arm: renesas: Add config option for R8A774C0 SoC
Add config support for RZ/G2E (a.k.a R8A774C0) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Biju Das
aca749a90f arm: renesas: Add config option for R8A774E1 SoC
Add config support for RZ/G2H(a.k.a R8A774E1) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
4e4c0e5e42 arm: renesas: Add config option for R8A774B1 SoC
Add config support for RZ/G2N(a.k.a R8A774B1) SoC.

Also fixed the alignment issue on R8A774A1 config.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
f4c5f97925 clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clock
Add RPC entry into the R8A774A1 clock driver tables.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
2f220c639a spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility string
Add fallback compatibility string for R-Car Gen3 and RZ/G2.

Also sorted the compatible string as per SoC ID.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Chunfeng Yun
0cd791ced9 MAINTAINERS: add USB driver to ARM MEDIATEK
Add MediaTek USB3 Dual-Role controller driver to ARM MEDIATEK,
and add myself as a maintainer for it.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00