Commit graph

778 commits

Author SHA1 Message Date
Stefan Roese
c680df7e84 mtd: nand: raw: Move CONFIG_SYS_NAND_USE_FLASH_BBT to Kconfig
Convert CONFIG_SYS_NAND_USE_FLASH_BBT to Kconfig, update defconfigs,
headers and whitelist.

Please note that this symbol already was used in Kconfig
(imply in CONFIG_NAND_ATMEL) which did not work, since this symbol was
not available in Kconfig. This changes now with this patch and all
boards with CONFIG_NAND_ATMEL will have BBT enabled. Which is what
I also need on my GARDENA AT91SAM based board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
[trini: Rework such that the configs are unchanged to start with]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-25 20:58:37 -04:00
Heinrich Schuchardt
51443f57d8 nand: davinci: avoid out of bounds array access
The array bounds have to be checked before accessing the array element.

Identified by cppcheck.

Fixes: 67ac6ffaee ("mtd: nand: davinci: add opportunity to write keystone U-boot image")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-31 13:08:07 -04:00
Bartosz Golaszewski
29d8eb3345 nand: davinci: add support for driver model
Extend the davinci NAND driver to support the driver model. For now this
doesn't add any device-tree parsing due to the fact that we can't access
the actual nand node on the device-tree - it's a subnode of the aemif
device and we don't have an aemif driver on davinci at the moment.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-07-29 17:58:52 -04:00
Bartosz Golaszewski
7bf9972643 nand: davinci: make davinci_nand_init() static
This function is only used within the driver itself. No need
to export it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-07-29 17:58:52 -04:00
Shyam Saini
1d43e24b94 i.MX6: nand: add nandbcb command for imx
Writing/updating boot image in nand device is not
straight forward in i.MX6 platform and it requires
boot control block(BCB) to be configured.

It becomes difficult to use uboot 'nand' command to
write BCB since it requires platform specific attributes
need to be taken care of.

It is even difficult to use existing msx-nand.c driver by
incorporating BCB attributes like mxs_dma_desc does
because it requires change in mtd and nand command.

So, cmd_nandbcb implemented in arch/arm/mach-imx

BCB contains two data structures, Firmware Configuration Block(FCB)
and Discovered Bad Block Table(DBBT). FCB has nand timings,
DBBT search area, page address of firmware.

On summary, nandbcb update will
- erase the entire partition
- create BCB by creating 2 FCB/DBBT block followed by
  1 FW block based on partition size and erasesize.
- fill FCB/DBBT structures
- write FW/SPL on FW1
- write FCB/DBBT in first 2 blocks

for nand boot, up on reset bootrom look for FCB structure in
first block's if FCB found the nand timings are loaded for
further reads. once FCB read done, DTTB will load and finally
firmware will be loaded which is boot image.

Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage
information.

Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
2019-07-19 14:51:25 +02:00
Patrick Delaunay
d99ea13cdf mtd: rawnand: stm32_fmc2: avoid warnings when building with W=1 option
This patch solves warnings detected by setting W=1 when building.

Warnings type detected:
 - [-Wsign-compare]
 - [-Wtype-limits]

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:57 +02:00
Mario Six
fe7d654d04 mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to Kconfig
Migrate the BR/OR settings to Kconfig. These must be known at compile
time, so cannot be configured via DT.

Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21 07:52:33 +02:00
Trevor Woerner
1001502545 CONFIG_SPL_SYS_[DI]CACHE_OFF: add
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-18 08:15:35 -04:00
Bartosz Golaszewski
a7fc3d7c68 nand: davinci: remove dead code for dm644x
The support for DaVinci DM* SoCs has been dropped. The code that used
to be relevant to dm644x is no longer needed. Remove it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-05-04 13:04:07 -04:00
Gregory CLEMENT
5f626e7849 mtd: nand: raw: Fix CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT behavior
The purpose of "mtd: nand: raw: allow to disable unneeded ECC layouts"
was to allow disabling the default ECC layouts if a driver is known to
provide its own ECC layout. However, this commit did the opposite and
disabled the default layout when it was _not_ selected.

It breaks all the NAND drivers not providing their own ECC layout this
patch fix this situation.

It was tested with the lpc32xx_nand_slc driver.

Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-26 18:58:20 -04:00
Philippe Reynes
f917438772 drivers: nand: brcmnand: add an option to read the write-protect from device tree
The option write-protect may only change on the kernel command line,
we add a property in the device tree to be more flexible.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 11:55:58 -04:00
Philippe Reynes
317d40eb01 drivers: nand: brcmnand: add parameter parameter-page-big-endian
The parameter page isn't always in big endian, so we add
an option to choose the endiannes of the parameter page.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 11:55:58 -04:00
Philippe Reynes
22daafba25 drivers: nand: brcmnand: add initial support
The driver brcmnand come from linux kernel 4.18.
Only SoC bcm6838 and bcm6858 are supported.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 11:55:58 -04:00
Boris Brezillon
9db29b300f mtd: nand: provide several helpers to do common NAND operations
Linux commit 97d90da8a88 ("mtd: nand: provide several helpers
to do common NAND operations")

This is part of the process of removing direct calls to ->cmdfunc()
outside of the core in order to introduce a better interface to execute
NAND operations.

Here we provide several helpers and make use of them to remove all
direct calls to ->cmdfunc(). This way, we can easily modify those
helpers to make use of the new ->exec_op() interface when available.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[miquel.raynal@free-electrons.com: rebased and fixed some conflicts]
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[Philippe Reynes: adapt code to u-boot and only keep new function]

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-22 11:55:58 -04:00
Simon Goldschmidt
ed784ac382 mtd: rawnand: denali: add reset handling
This adds reset handling to the devicetree-enabled Denali NAND driver.

For backwards compatibility, only a warning is printed when failing to
get reset handles.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-04-17 22:20:16 +02:00
Tom Rini
216800acf1 Merge branch 'master' of git://git.denx.de/u-boot-spi
Conflicts:
	arch/arm/dts/armada-385-amc.dts
	arch/arm/dts/armada-xp-theadorable.dts
	arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-14 00:03:06 -04:00
Christophe Kerello
7bb75023a7 mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver
The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.

This patch adds the polling mode, a basic mode that do not need
any DMA channels.

Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
 - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8)
 - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
 - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC
   based on Hamming)

This patch has been tested on Micron MT29F8G08ABACAH4.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
2019-04-12 16:09:13 +02:00
Stefan Roese
d67fb265d1 mtd: spinand: Sync GigaDevice GD5F1GQ4UExxG with latest Linux version
This patch sync's the U-Boot SPI NAND GigaDevice GD5F1GQ4UExxG support
with the latest Linux version (v5.0-rc3) plus the chip supported posted
on the MTD list. Only the currently in U-Boot available chip is
supported with this sync.

The changes for the GD5F1GQ4UExxG are:
- Name of NAND device changed to better reflect the real part
- OOB layout changed to only reserve 1 byte for BBT
- Use ECC caps 8bits/512bytes instead of 8bits/2048bytes
- Enhanced ecc_get_status() function to determine and report
  a more fine grained bit error status

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-12 10:54:11 +05:30
Adam Ford
d46d27d3b6 MTD: mxs_nand_spl: Redo the way nand_init initializes
Currently the spl system calls nand_init which does nothing.
It isn't until an attempt to load from NAND that it gets initialized.
Subsequent attempts to load just skip the initialization  because
NAND is already initialized.

This moves the contents of mxs_nand_init to nand_init.  In the event
of an error, it clears the number of nand chips found.  Any
attempts to use nand will check if there are nand chips available
instead of actually doing the initialization at that time. If there
are none, it will return an error to the higher level calls.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-03-13 09:14:35 +01:00
Adam Ford
04568bd0b6 MTD: nand: mxs_nand: Allow driver to auto setup ECC in SPL
The initialization of the NAND in SPL hard-coded ecc.bytes,
ecc.size, and ecc.strength which may work for some NAND parts,
but it not appropriate for others.  With the pending patch
"mxs_nand: Fix BCH read timeout error on boards requiring ECC"
the driver can auto configure the ECC when these entries are
blank.  This patch has been tested in NAND flash with oob 64
and oob 128.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 12:42:13 +01:00
Adam Ford
5645df9e00 MTD: NAND: mxs_nand_init_dma: Make mxs_nand_init_dma static
mxs_nand_init_dma is only referenced from mxs_nand.c.  It's not
referenced in any headers or outside code, so this patch
defines it as static.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-15 12:36:44 +01:00
Adam Ford
5ae585ba3a MTD: mxs_nand: Fix BCH read timeout error on boards requiring ECC
The LogicPD board uses a Micron Flash with ECC.  To boot this from
SPL, the ECC needs to be correctly configured or the BCH engine
times out.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 12:36:08 +01:00
Adam Ford
96d0be07e7 MTD: nand: mxs_nand_spl: Fix empty function pointer for BBT
The initialization function calls a nand_chip.scan_bbt(mtd) but
scan_bbt is never initialized resulting in an undefined function
pointer.  This will direct the function pointer to nand_default_bbt
defined in the same file.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28 20:55:46 +01:00
T Karthik Reddy
97fca6a146 mtd: nand: arasan_nfc: Add support for nand multi chip select
This patch adds support for nand multi chip select.
Also adding CONFIG_SYS_NAND_MAX_CHIPS to Kconfig to specify maximum number
of nand chips.

Signed-off-by: Tummala Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24 10:03:42 +01:00
Derald D. Woods
49ad40298c ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig
This commit converts the following items to Kconfig:

CONFIG_ATMEL_NAND_HWECC
CONFIG_ATMEL_NAND_HW_PMECC
CONFIG_PMECC_CAP
CONFIG_PMECC_SECTOR_SIZE
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

[PMECC References]
https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure
https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap

[Mailing List Thread]
https://lists.denx.de/pipermail/u-boot/2018-December/350666.html

Fixes: 5541543f ("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment")
[trini: Make the migration be size neutral and possibly not fix the
above in all cases]
Reported-by: Daniel Evans <photonthunder@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-01-21 08:36:11 -05:00
Stefan Agner
a38c3af868 mtd: nand: raw: allow to disable unneeded ECC layouts
Each ECC layout consumes about 2984 bytes in the .data section. Allow
to disable the default ECC layouts if a driver is known to provide its
own ECC layout.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-01-16 16:14:45 -05:00
Tom Rini
695f67b5b3 Merge branch 'master' of git://git.denx.de/u-boot-spi 2019-01-02 14:20:29 -05:00
Nikolai Zhubr
cdf72c188c mtd: nand: raw: Add Hynix H27UBG8T2BTR id table
This patch adds Hynix H27UBG8T2BTR id table as part of raw nand,
these chips were available in some A20-olinuxino-micro boards.

Signed-off-by: Nikolai Zhubr <n-a-zhubr@yandex.ru>
[jagan: add proper commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-02 00:58:16 +05:30
Tom Rini
522e035441 imx for 2019.01
- introduce support for i.MX8M
 - fix size limit for Vhybrid / pico boards
 - several board fixes
 - w1 driver for MX2x / MX5x
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Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x
2019-01-01 10:01:00 -05:00
Lukasz Majewski
acdf10e179 nand: vybrid: Extend the vf610 NFC NAND driver to support device tree (and DM)
This commit adds support for device tree and enumeration via device model
for the Vybrid's NFC NAND driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-01 14:12:18 +01:00
Lukasz Majewski
8a12d127d7 Kconfig: Add entry for VF610 NAND NFC device tree aware driver
This commit provides code to add proper entry to Kconfig to enable
support for VF610 device tree aware driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-01-01 14:12:18 +01:00
Lukasz Majewski
254409dbe8 nand: vybrid: Use calloc() instead of malloc() to allocate struct nfc
Without this change it is possible that Vybrid's NFC driver malloc() call
will obtain some memory used (and correctly free'd) by some previous
driver (in this case pinctrl for Vybrid).

As a result some fields of struct nfc - in out case mtd->_get_device - are
"pre initialized" with some random values.

On the latter stage of booting, when e.g. somebody calls 'mtdparts default'
the "data abort" is observed when __get_mtd_device() function is called.

The mtd->_get_device pointer is not NULL and wrong value is referenced.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-01 14:12:18 +01:00
Masahiro Yamada
9d43649a77 mtd: rawnand: denali: fix a race condition when DMA is kicked
Based on Linux commit cf51e4b9c34407bf0c3d9b582b7837e047e1df47

Add the register read-back, commenting why this is necessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-29 11:38:37 +09:00
Masahiro Yamada
8ccfbfb3e1 mtd: rawnand: denali: optimize timing parameters for data interface
Based on Linux commit 1dfac31a5a63ac04a9b5fbc3f5105a586560f191

This commit improves the ->setup_data_interface() hook.

The denali_setup_data_interface() needs the frequency of clk_x
and the ratio of clk_x / clk.

The latter is currently hardcoded in the driver, like this:

  #define DENALI_CLK_X_MULT       6

The IP datasheet requires that clk_x / clk be 4, 5, or 6.  I just
chose 6 because it is the most defensive value, but it is not optimal.
By getting the clock rate of both "clk" and "clk_x", the driver can
compute the timing values more precisely.

To not break the existing platforms, the fallback value, 50 MHz is
provided.  It is true for all upstreamed platforms.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-29 11:38:37 +09:00
Masahiro Yamada
a13fe7afe9 mtd: rawnand: denali_dt: add more clocks based on IP datasheet
Based on Linux commit 6f1fe97bec349a1fd6c5a8c7c5998d759fe721d5

Currently, denali_dt.c requires a single anonymous clock, but
the Denali User's Guide requires three clocks for this IP:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

This commit supports these named clocks to represent the real hardware.

For the backward compatibility, the driver still accepts a single clock
just as before.  The clk_x_rate is taken from the clock driver again if
the named clock "clk_x" is available.  This will happen only for future
DT, hence the existing DT files are not affected.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-29 11:38:36 +09:00
Tom Rini
9450ab2ba8 Merge branch 'master' of git://git.denx.de/u-boot-spi
- Various MTD fixes from Boris
- Zap various unused / legacy paths.
- pxa3xx NAND update from Miquel

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-05 15:06:24 -05:00
Martin Lund
1cefca71d2 mtd: nand: Arasan: Add subpage configuration support
Add support for disabling subpage write support via
CONFIG_SYS_NAND_NO_SUBPAGE_WRITE.

Currently the Linux Arasan driver does not support subpage writes and in
case of running UBI and accessing the same UBI volume from both U-Boot
and Linux it is required to have the same subpage write configuration
else the location of the UBI headers (EC + VID) will be misaligned
(subpage vs page) and incompatible. Hence the need for disabling
subpage write support in the U-Boot Arasan NAND driver.

Signed-off-by: Martin Lund <malu@gomspace.com>
Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:54 +01:00
Miquel Raynal
c907464a0a mtd: rawnand: pxa3xx: fix 2kiB pages with 8b strength chips layout
The initial layout for such NAND chips was the following:

+----------------------------------------------------------------------------+
| 1024 (data) | 30 (ECC) | 1024 (data) | 30 (ECC) | 32 (free OOB) | 30 (ECC) |
+----------------------------------------------------------------------------+

This layout has a weakness: reading empty pages trigger ECC errors
(this is expected), but the hardware ECC engine tries to correct the
data anyway and creates itself bitflips, hence bitflips are detected
in erased pages while actually there are none in the NAND chip.

Two solutions have been found at the same time. One was to enlarge the
free OOB area to 64 bytes, changing the layout to be:

+----------------------------------------------------------------------------+
| 1024 (data) | 30 (ECC) | 1024 (data) | 30 (ECC) | 64 (free OOB) | 30 (ECC) |
+----------------------------------------------------------------------------+
                                                    ^^

The very big drawbacks of this solution are:
1/ It prevents booting from NAND.
2/ The current Linux driver (marvell_nand) does not have such problem
because it already re-reads possible empty pages in raw mode before
checking for bitflips. Using different layouts in U-Boot and Linux
would simply not work.

As this driver does support raw reads now and uses it to check for
empty pages, let's forget about this broken hack and return to the
initial layout with only 32 free OOB bytes.

Fixes: ac56a3b30c ("mtd: nand: pxa3xx: add support for 2KB 8-bit flash")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-22 11:38:13 +05:30
Miquel Raynal
af61ea27f5 mtd: nand: pxa3xx: re-read a page in raw mode on uncorrectable error
This only applies on BCH path.

When an empty page is read, it triggers an uncorrectable error. While
this is expected, the ECC engine might produce itself bitflips in the
read data under certain layouts. To overcome this situation, always
re-read the entire page in raw mode and check for the whole page to be
empty.

Also report the right number of bitflips if there are any.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-22 11:38:05 +05:30
Miquel Raynal
6293b0361d mtd: nand: pxa3xx: add raw read support
Raw read support is added by editing a few code sections:

    ->handle_data_pio() includes the ECC bytes that are not consumed
    anymore by the ECC engine.

    ->prepare_set_command() is changed so that the ECC bytes are
    requested as part of the data I/O length.

    ->drain_fifo() shall also avoid checking the R/B pin too often
    when in raw mode.

    ->read_page_raw()/->read_oob_raw() are written from scratch.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-22 11:37:44 +05:30
Vladimir Zapolskiy
44cdfc0ece mtd: nand: lpc32xx slc: disable DMA support in SPL builds
Testing and analysis shows that at the moment LPC32xx NAND SLC driver
can not get PL080 DMA backbone support in SPL build, because SPL NAND
loaders operate with subpage (ECC step to be precisely) reads, and
this is not supported in the NAND SLC + DMA + hardware ECC calculation
bundle.

The change removes a cautious build time warning and explicitly
disables DMA flavour of the driver for SPL builds, to reduce the
amound of #ifdef sections the code blocks are minimally reorganized.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2018-11-16 13:34:37 -05:00
Vladimir Zapolskiy
a098ce2142 mtd: nand: lpc32xx mlc: predefine number of NAND chips to support
Build option CONFIG_SYS_MAX_NAND_CHIPS is used by NXP LPC32xx NAND MLC
driver only, as a preparation for potential removal or replacement of
the option the change predefines CONFIG_SYS_MAX_NAND_CHIPS to 1, same
value is used by the single user Work Microwave Work 92105 board, thus
it will be safe now to remove the option as a board specific one.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-11-16 13:34:36 -05:00
Bin Meng
ed5df0852f nand: atmel: Initialize pmecc smu with correct size
Currently in pmecc_get_sigma(), the code tries to clear the memory
pointed by smu with wrong size 'sizeof(int16_t) * ARRAY_SIZE(smu)'.
Since smu is actually a pointer, not an array, so ARRAY_SIZE(smu)
does not generate correct size to be cleared.

In fact, GCC 8.1.0 reports a warning against it:

error: division 'sizeof (int16_t * {aka short int *}) / sizeof (int16_t
{aka short int})' does not compute the number of array elements
[-Werror=sizeof-pointer-div]

Fix it by using the correct size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-10-22 09:18:49 -04:00
Stefan Roese
9e5c2a755a mtd: nand: spi: Add Gigadevice SPI NAND support
This patch adds support for Gigadevices SPI NAND device to the new SPI
NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC
device is supported.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Jagan Teki <jagan@openedev.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-10-04 18:24:24 +05:30
Miquel Raynal
515d021261 mtd: spinand: Add initial support for the MX35LF2GE4AB chip
Add support for the MX35LF2GE4AB chip, which is similar to its cousin
MX35LF1GE4AB, with two planes instead of one.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Boris Brezillon
6f041ccabb mtd: spinand: Add initial support for the MX35LF1GE4AB chip
Add minimal support for the MX35LF1GE4AB SPI NAND chip.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Frieder Schrempf
3181c0a622 mtd: spinand: Add initial support for Winbond W25M02GV
Add support for the W25M02GV chip.

Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Peter Pan
883d8778ae mtd: spinand: Add initial support for Micron MT29F2G01ABAGD
Add a basic driver for Micron SPI NANDs. Only one device is supported
right now, but the driver will be extended to support more devices
afterwards.

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Peter Pan
0a6d6bae03 mtd: nand: Add core infrastructure to support SPI NANDs
Add a SPI NAND framework based on the generic NAND framework and the
spi-mem infrastructure.

In its current state, this framework supports the following features:

- single/dual/quad IO modes
- on-die ECC

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30
Boris Brezillon
b95db8d33a mtd: nand: Add core infrastructure to deal with NAND devices
Add an intermediate layer to abstract NAND device interface so that
some logic can be shared between SPI NANDs, parallel/raw NANDs,
OneNANDs, ...

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-20 20:10:49 +05:30