Commit graph

22 commits

Author SHA1 Message Date
Tom Rini
19f6576007 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-01 09:10:04 -05:00
Marek Vasut
a80e0e7711 ARM: imx: Enable kaslrseed command on DH i.MX8M Plus DHCOM
Linux 6.6.y with KASLR enabled would print the following message on boot:
"
KASLR disabled due to lack of seed
"
Enable the 'kaslrseed' command so a random number seed can be pulled
from CAAM and inserted into the /chosen node 'kaslr-seed' property of
Linux kernel DT before boot, thus letting KASLR work properly.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2024-01-22 08:40:02 -03:00
Marek Vasut
4dd80cb09e ARM: imx: Enable SPL_BOARD_INIT on DH i.MX8M Plus DHCOM
The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init()
during the SPL start up. On this particular system, spl_board_init()
is used to reconfigure GIC clock parent to PLL2 500M, which is the
configuration expected by the Linux kernel. Enable SPL_BOARD_INIT .

Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
allow to change it. Should set the clock after PMIC setting done.
Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
ND VDD_SOC.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2024-01-22 08:38:48 -03:00
Tom Rini
42fb448a20 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-03 09:26:16 -05:00
Tom Rini
93a0138acb Prepare v2024.01-rc6
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmWVa0gACgkQFHw5/5Y0
 tyyxaAv/XwG8mzltTwMHc65IHmeupJLhBPBJgrZyZPlHRWNThSKBcbtTKnJIxN/j
 ZAakyMFykkZCs+xfpckjzyY9CA2B5pkZ1RMKj5AgiWOH3+vbCPN92/wzs+NVpN78
 ek1Ht2McIM51pdLYe50hYuqIU/Y8rWsptpK9/t2rdGSa79G70uo3DTGNYVyGcLNF
 b63B42FLnu11+MkyfN7z2Q3y0OlKpT/oZHb6R4rWNWNQqDbpficpEvoJdA1LzeAg
 GouCZ7Ib1qffoydbj1wruYT7Pkg9AsPs1tNa2eENJldfthlx9PFrW4be1t8bRput
 WnpbSbxRBw1sS8dukjCi0st+lhUNyuapT2J7hmtuXSMVprxK0UzQMbdGo9suxSlT
 DwTuTsNvwGzIk5E4SRZZI+xSUqpeCKnnVC7OLcqGKSAsoZIv5s5Fq/VgIIQ7gzNY
 LA+kdSjVeiKfsPzXCXCvILMqffwS8J9zIYdoxmq4o9XsmksabDCDUZpEy9IQ3gbB
 6MPxZgnj
 =Sqkn
 -----END PGP SIGNATURE-----

Merge tag 'v2024.01-rc6' into next

Prepare v2024.01-rc6
2024-01-03 09:22:47 -05:00
Tom Rini
b2cbf968dd configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-03 09:09:56 -05:00
Tom Rini
1373ffde52 Prepare v2024.01-rc5
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmWARagACgkQFHw5/5Y0
 tyyB/gv9HPhYpvmGi8GcqmlQ2Y2fDr5c5Tti0BUMtMzLGM/J8CEcfSF4oPmdPy3f
 NHHWlCTzO8HHtoCZg1h5NknbrFaYVFdrKAV/Vy7JDH9J+/uEd39i6UJUO3TkIcpr
 Ykb6eXL1OdTnjVFOs3VPcLc93No3Rb3chC1aqb447r1rgWc+uqyZcQrdDMyko6sh
 e0l+JRlpi0xprwF5/THKbNdnU4XrryRtienpFclzSwrAzz3vuoUteqRwQY7auttz
 RQMlTQooV1D73bOc2kZjLKH5xXdjU3bT9PetR/mHkzCDa6xbNy/OWxnpS8b4+dVh
 cjTpeHcgDIRjtOv9kmi4fZPt4865KxJ5jk8WCCfOwPRlgUe0q3tJgEQMBy3fEgNw
 BmnzLVqpHAAMQZDx93D8RxdzyiInGATIMfdFFPQ04R/UqNCO3XmSnHno4CZ/lm4w
 fjiP7NgwKe7rnXNbhCdBEmZqfwb7MA5RQ5/zxsdbeIuk5tOIMi7nBa+CNLUGD7bh
 6QGsTrYf
 =lS+J
 -----END PGP SIGNATURE-----

Merge tag 'v2024.01-rc5' into next

Prepare v2024.01-rc5
2023-12-18 09:55:32 -05:00
Marek Vasut
31757f2bea ARM: imx: Update DRAM timings with inline ECC on DH i.MX8MP DHCOM SoM
Import DRAM timings generated by the DDR tool 3.31 which introduce assorted
tweaks to the DRAM controller settings. Furthermore, enable DBI to improve
noise resilience of the DRAM bus by reducing the number of bit changes on
the bus.

Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors
reported by EDAC . It is not entirely clear why the slightly faster setting
does produce sporadic correctable errors, while this one does not, but this
could be related to simpler PLL setting at 3600 MTps.

Enable inline ECC which is necessary to detect ECC errors and collect
statistics by the EDAC driver in Linux. This reduces the DRAM size by
64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available
DRAM size becomes 3.5 GiB and for 2 GiB device the available DRAM size
becomes 1.8 GiB.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-12-16 07:45:07 -03:00
Marek Vasut
f4d15df831 ARM: imx: Enable CAAM on DH i.MX8M Plus DHCOM
Enable CAAM in U-Boot to make crypto available early in the boot process.

This has a side-effect that in case an older kernel version contains a
broken CAAM initialization timeout code, initialization in bootloader
will help that old kernel version function correctly.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 15:29:08 -03:00
Marek Vasut
91613b1539 arm64: imx8mp: Enable TCP, IPv6, wget on DH i.MX8MP DHCOM
Enable support for TCP protocol, wget, and IPv6 on this platform.
The former two allow users download payload into the U-Boot from
a web server, which may be more convenient or easier to set up
than TFTP server. The later is enabled to future proof the IP
stack on this platform.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14 06:20:32 -03:00
Tom Rini
4bb6f61220 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-23 15:08:23 -04:00
Marek Vasut
9de599ec3d arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200
The current imx8mp-dhcom-som.dtsi describes prototype rev.100 SoM,
update the DT to describe production rev.200 SoM which brings the
following changes:
- Fast SoC GPIOs exposed on the SoM edge connector
- Slow GPIOs like component resets moved to I2C GPIO expander
- ADC upgraded from TLA2024 to ADS1015 with conversion interrupt
- EEPROM size increased from 256 B to 4 kiB

Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-16 16:25:10 +02:00
Marek Vasut
ad1158c50e arm64: dts: imx8mp: Switch to DT overlays for i.MX8MP DHCOM SoM
Add DT overlays to support additional DH i.MX8MP DHCOM SoM 660-100
population options with 1x or 2x RMII PHY mounted on PDK2 or PDK3
carrier boards.

Use SPL DTO support to apply matching SoM specific DTO to cater
for the SoM differences. Remove ad-hoc patching of control DT from
fdtdec_board_setup().

Signed-off-by: Marek Vasut <marex@denx.de>
2023-10-16 16:25:10 +02:00
Simon Glass
82e26e0d68 spl: Use CONFIG_SPL... instead of CONFIG_..._SPL_...
We like to put the SPL first so it is clear that it relates to SPL. Rename
various malloc-related options which have crept in, to stick to this
convention.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-10-06 14:38:11 -04:00
Tom Rini
ac897385bb Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-02 10:55:44 -04:00
Tom Rini
ba6d575ee0 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-02 10:35:27 -04:00
Marek Vasut
bd7606d142 ARM: imx: Use default SAVED_DRAM_TIMING_BASE on DH i.MX8M Plus DHCOM
Use default SAVED_DRAM_TIMING_BASE as that is what upstream TFA expects.
Without this change, the board will fail to suspend/resume e.g. in Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-09-04 10:21:20 +02:00
Tom Rini
a077ac13d0 Kconfigs: Correct default of "0" on hex type entries
It is not a parse error to have a default value of "0" for a "hex" type
entry, instead of "0x0".  However, "0" and "0x0" are not treated the
same even by the tools themselves. Correct this by changing the default
value from "0" to "0x0" for all hex type questions that had the
incorrect default. Fix one instance (in two configs) of a default of "0"
being used on a hex question to be "0x0". Remove the cases where a
defconfig had set a value of "0x0" to be used as the default had been
"0".

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-09 09:21:42 -04:00
Tom Rini
df8967435a configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-08-07 15:17:12 -04:00
Tom Rini
c90e18932b configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-29 10:43:26 -04:00
Tom Rini
c960c0fd38 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-01 11:50:26 -04:00
Marek Vasut
3a125806f1 ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM on PDK3
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK3 carrier board.
Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD,
SPI NOR and USB 3.0 host.

Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30 08:40:27 +02:00