mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-16 06:46:59 +00:00
Merge branch 'mpc86xx'
This commit is contained in:
Jon Loeliger
commit
c926a82d82
5 changed files with 520 additions and 478 deletions
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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|||
|
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o oftree.o
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OBJS := $(BOARD).o pixis.o oftree.o
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SOBJS := init.o
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|
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$(LIB): $(OBJS) $(SOBJS)
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|
|
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@ -25,6 +25,7 @@
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_86xx.h>
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|
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@ -35,20 +36,23 @@
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extern void ft_cpu_setup(void *blob, bd_t *bd);
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#endif
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#include "pixis.h"
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|
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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extern long int spd_sdram(void);
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#if defined(CONFIG_SPD_EEPROM)
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#include "spd_sdram.h"
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#endif
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void local_bus_init(void);
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void sdram_init(void);
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long int fixed_sdram(void);
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int board_early_init_f (void)
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{
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return 0;
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return 0;
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}
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int checkboard (void)
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@ -57,41 +61,34 @@ int checkboard (void)
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#ifdef CONFIG_PCI
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile ccsr_pex_t *pex1 = &immap->im_pex1;
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile ccsr_pex_t *pex1 = &immap->im_pex1;
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
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uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
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uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
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uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
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if ((io_sel==2 || io_sel==3 || io_sel==5 \
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|| io_sel==6 || io_sel==7 || io_sel==0xF)
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
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debug ("PCI-EXPRESS 1: %s \n",
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pex1_agent ? "Agent" : "Host");
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debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
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if (pex1->pme_msg_det) {
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pex1->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",
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pex1->pme_msg_det);
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}
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debug ("\n");
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} else {
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printf ("PCI-EXPRESS 1: Disabled\n");
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}
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if ((io_sel == 2 || io_sel == 3 || io_sel == 5
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|| io_sel == 6 || io_sel == 7 || io_sel == 0xF)
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
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debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
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debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
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if (pex1->pme_msg_det) {
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pex1->pme_msg_det = 0xffffffff;
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debug(" with errors. Clearing. Now 0x%08x",
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pex1->pme_msg_det);
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}
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debug ("\n");
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} else {
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puts("PCI-EXPRESS 1: Disabled\n");
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}
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#else
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printf("PCI-EXPRESS1: Disabled\n");
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puts("PCI-EXPRESS1: Disabled\n");
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#endif
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/*
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* Initialize local bus.
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*/
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local_bus_init();
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return 0;
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}
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@ -100,7 +97,6 @@ long int
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initdram(int board_type)
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{
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long dram_size = 0;
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extern long spd_sdram (void);
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram ();
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@ -112,7 +108,7 @@ initdram(int board_type)
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puts(" DDR: ");
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return dram_size;
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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@ -125,34 +121,6 @@ initdram(int board_type)
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_lbc_t *lbc = &immap->im_lbc;
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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/*
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* Errata LBC11.
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* Fix Local Bus clock glitch when DLL is enabled.
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*
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* If localbus freq is < 66Mhz, DLL bypass mode must be used.
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* If localbus freq is > 133Mhz, DLL can be safely enabled.
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* Between 66 and 133, the DLL is enabled with an override workaround.
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*/
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get_sys_info(&sysinfo);
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clkdiv = lbc->lcrr & 0x0f;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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}
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#if defined(CFG_DRAM_TEST)
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int testdram(void)
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{
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@ -160,7 +128,7 @@ int testdram(void)
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf("SDRAM test phase 1:\n");
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puts("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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@ -171,7 +139,7 @@ int testdram(void)
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}
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}
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printf("SDRAM test phase 2:\n");
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puts("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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@ -182,7 +150,7 @@ int testdram(void)
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}
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}
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||||
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printf("SDRAM test passed.\n");
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puts("SDRAM test passed.\n");
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return 0;
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}
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#endif
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@ -207,9 +175,9 @@ long int fixed_sdram(void)
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ddr->sdram_mode_1 = CFG_DDR_MODE_1;
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ddr->sdram_mode_2 = CFG_DDR_MODE_2;
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ddr->sdram_interval = CFG_DDR_INTERVAL;
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ddr->sdram_data_init = CFG_DDR_DATA_INIT;
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ddr->sdram_data_init = CFG_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
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ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
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ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
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ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
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#if defined (CONFIG_DDR_ECC)
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@ -217,7 +185,7 @@ long int fixed_sdram(void)
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ddr->err_sbe = 0x00ff0000;
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#endif
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asm("sync;isync");
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udelay(500);
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#if defined (CONFIG_DDR_ECC)
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@ -228,7 +196,7 @@ long int fixed_sdram(void)
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ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
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#endif
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asm("sync; isync");
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udelay(500);
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#endif
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return CFG_SDRAM_SIZE * 1024 * 1024;
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@ -281,15 +249,113 @@ ft_board_setup(void *blob, bd_t *bd)
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int len;
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ft_cpu_setup(blob, bd);
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p = ft_get_prop(blob, "/memory/reg", &len);
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if (p != NULL) {
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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}
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#endif
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void
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mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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char cmd;
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ulong val;
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ulong corepll;
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/*
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* No args is a simple reset request.
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*/
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if (argv <= 0) {
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out8(PIXIS_BASE + PIXIS_RST, 0);
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/* not reached */
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}
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cmd = argv[1][1];
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switch (cmd) {
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case 'f': /* reset with frequency changed */
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if (argc < 5)
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goto my_usage;
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read_from_px_regs(0);
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val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
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corepll = strfractoint(argv[3]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
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if (val == 3) {
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puts("Setting registers VCFGEN0 and VCTL\n");
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read_from_px_regs(1);
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puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
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set_px_go();
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} else
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goto my_usage;
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while (1); /* Not reached */
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|
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case 'l':
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if (argv[2][1] == 'f') {
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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/* reset with frequency changed */
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val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
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corepll = strfractoint(argv[4]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10));
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if (val == 3) {
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puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs(1);
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read_from_px_regs_altbank(1);
|
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puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
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||||
set_px_go_with_watchdog();
|
||||
} else
|
||||
goto my_usage;
|
||||
|
||||
while(1); /* Not reached */
|
||||
|
||||
} else if(argv[2][1] == 'd'){
|
||||
/*
|
||||
* Reset from alternate bank without changing
|
||||
* frequencies but with watchdog timer enabled.
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
|
||||
set_px_go_with_watchdog();
|
||||
while(1); /* Not reached */
|
||||
|
||||
} else {
|
||||
/*
|
||||
* Reset from next bank without changing
|
||||
* frequency and without watchdog timer enabled.
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
if(argc > 2)
|
||||
goto my_usage;
|
||||
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Resetting board to boot from the other bank....\n");
|
||||
set_px_go();
|
||||
}
|
||||
|
||||
default:
|
||||
goto my_usage;
|
||||
}
|
||||
|
||||
my_usage:
|
||||
puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
|
||||
puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
|
||||
puts(" reset altbank [wd]\n");
|
||||
puts("For example: reset cf 40 2.5 10\n");
|
||||
puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
|
||||
}
|
||||
|
|
|
|||
324
board/mpc8641hpcn/pixis.c
Normal file
324
board/mpc8641hpcn/pixis.c
Normal file
|
|
@ -0,0 +1,324 @@
|
|||
/*
|
||||
* Copyright 2006 Freescale Semiconductor
|
||||
* Jeff Brown
|
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <command.h>
|
||||
#include <asm/cache.h>
|
||||
#include <mpc86xx.h>
|
||||
|
||||
#include "pixis.h"
|
||||
|
||||
|
||||
/*
|
||||
* Per table 27, page 58 of MPC8641HPCN spec.
|
||||
*/
|
||||
int set_px_sysclk(ulong sysclk)
|
||||
{
|
||||
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
|
||||
|
||||
switch (sysclk) {
|
||||
case 33:
|
||||
sysclk_s = 0x04;
|
||||
sysclk_r = 0x04;
|
||||
sysclk_v = 0x07;
|
||||
sysclk_aux = 0x00;
|
||||
break;
|
||||
case 40:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x20;
|
||||
sysclk_aux = 0x01;
|
||||
break;
|
||||
case 50:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x2A;
|
||||
sysclk_aux = 0x02;
|
||||
break;
|
||||
case 66:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x04;
|
||||
sysclk_v = 0x04;
|
||||
sysclk_aux = 0x03;
|
||||
break;
|
||||
case 83:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x4B;
|
||||
sysclk_aux = 0x04;
|
||||
break;
|
||||
case 100:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x5C;
|
||||
sysclk_aux = 0x05;
|
||||
break;
|
||||
case 134:
|
||||
sysclk_s = 0x06;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x3B;
|
||||
sysclk_aux = 0x06;
|
||||
break;
|
||||
case 166:
|
||||
sysclk_s = 0x06;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x4B;
|
||||
sysclk_aux = 0x07;
|
||||
break;
|
||||
default:
|
||||
printf("Unsupported SYSCLK frequency.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
vclkh = (sysclk_s << 5) | sysclk_r ;
|
||||
vclkl = sysclk_v;
|
||||
|
||||
out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
|
||||
out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
|
||||
|
||||
out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int set_px_mpxpll(ulong mpxpll)
|
||||
{
|
||||
u8 tmp;
|
||||
u8 val;
|
||||
|
||||
switch (mpxpll) {
|
||||
case 2:
|
||||
case 4:
|
||||
case 6:
|
||||
case 8:
|
||||
case 10:
|
||||
case 12:
|
||||
case 14:
|
||||
case 16:
|
||||
val = (u8)mpxpll;
|
||||
break;
|
||||
default:
|
||||
printf("Unsupported MPXPLL ratio.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
|
||||
tmp = (tmp & 0xF0) | (val & 0x0F);
|
||||
out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int set_px_corepll(ulong corepll)
|
||||
{
|
||||
u8 tmp;
|
||||
u8 val;
|
||||
|
||||
switch ((int)corepll) {
|
||||
case 20:
|
||||
val = 0x08;
|
||||
break;
|
||||
case 25:
|
||||
val = 0x0C;
|
||||
break;
|
||||
case 30:
|
||||
val = 0x10;
|
||||
break;
|
||||
case 35:
|
||||
val = 0x1C;
|
||||
break;
|
||||
case 40:
|
||||
val = 0x14;
|
||||
break;
|
||||
case 45:
|
||||
val = 0x0E;
|
||||
break;
|
||||
default:
|
||||
printf("Unsupported COREPLL ratio.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
|
||||
tmp = (tmp & 0xE0) | (val & 0x1F);
|
||||
out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
void read_from_px_regs(int set)
|
||||
{
|
||||
u8 mask = 0x1C;
|
||||
u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
|
||||
|
||||
if (set)
|
||||
tmp = tmp | mask;
|
||||
else
|
||||
tmp = tmp & ~mask;
|
||||
out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
|
||||
}
|
||||
|
||||
|
||||
void read_from_px_regs_altbank(int set)
|
||||
{
|
||||
u8 mask = 0x04;
|
||||
u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
|
||||
|
||||
if (set)
|
||||
tmp = tmp | mask;
|
||||
else
|
||||
tmp = tmp & ~mask;
|
||||
out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
|
||||
}
|
||||
|
||||
|
||||
void set_altbank(void)
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
|
||||
tmp ^= 0x40;
|
||||
|
||||
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
|
||||
}
|
||||
|
||||
|
||||
void set_px_go(void)
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
|
||||
tmp = tmp & 0x1E;
|
||||
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
|
||||
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
|
||||
tmp = tmp | 0x01;
|
||||
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
|
||||
}
|
||||
|
||||
|
||||
void set_px_go_with_watchdog(void)
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
|
||||
tmp = tmp & 0x1E;
|
||||
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
|
||||
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
|
||||
tmp = tmp | 0x09;
|
||||
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
|
||||
}
|
||||
|
||||
|
||||
int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
|
||||
tmp = tmp & 0x1E;
|
||||
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
|
||||
|
||||
/* setting VCTL[WDEN] to 0 to disable watch dog */
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
|
||||
tmp &= ~ 0x08;
|
||||
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
U_BOOT_CMD(
|
||||
diswd, 1, 0, disable_watchdog,
|
||||
"diswd - Disable watchdog timer \n",
|
||||
NULL
|
||||
);
|
||||
|
||||
|
||||
/*
|
||||
* This function takes the non-integral cpu:mpx pll ratio
|
||||
* and converts it to an integer that can be used to assign
|
||||
* FPGA register values.
|
||||
* input: strptr i.e. argv[2]
|
||||
*/
|
||||
|
||||
ulong strfractoint(uchar *strptr)
|
||||
{
|
||||
int i, j, retval;
|
||||
int mulconst;
|
||||
int intarr_len = 0, decarr_len = 0, no_dec = 0;
|
||||
ulong intval = 0, decval = 0;
|
||||
uchar intarr[3], decarr[3];
|
||||
|
||||
/* Assign the integer part to intarr[]
|
||||
* If there is no decimal point i.e.
|
||||
* if the ratio is an integral value
|
||||
* simply create the intarr.
|
||||
*/
|
||||
i = 0;
|
||||
while (strptr[i] != 46) {
|
||||
if (strptr[i] == 0) {
|
||||
no_dec = 1;
|
||||
break;
|
||||
}
|
||||
intarr[i] = strptr[i];
|
||||
i++;
|
||||
}
|
||||
|
||||
/* Assign length of integer part to intarr_len. */
|
||||
intarr_len = i;
|
||||
intarr[i] = '\0';
|
||||
|
||||
if (no_dec) {
|
||||
/* Currently needed only for single digit corepll ratios */
|
||||
mulconst=10;
|
||||
decval = 0;
|
||||
} else {
|
||||
j = 0;
|
||||
i++; /* Skipping the decimal point */
|
||||
while ((strptr[i] > 47) && (strptr[i] < 58)) {
|
||||
decarr[j] = strptr[i];
|
||||
i++;
|
||||
j++;
|
||||
}
|
||||
|
||||
decarr_len = j;
|
||||
decarr[j] = '\0';
|
||||
|
||||
mulconst = 1;
|
||||
for (i = 0; i < decarr_len; i++)
|
||||
mulconst *= 10;
|
||||
decval = simple_strtoul(decarr, NULL, 10);
|
||||
}
|
||||
|
||||
intval = simple_strtoul(intarr, NULL, 10);
|
||||
intval = intval * mulconst;
|
||||
|
||||
retval = intval + decval;
|
||||
|
||||
return retval;
|
||||
}
|
||||
33
board/mpc8641hpcn/pixis.h
Normal file
33
board/mpc8641hpcn/pixis.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright 2006 Freescale Semiconductor
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
extern int set_px_sysclk(ulong sysclk);
|
||||
extern int set_px_mpxpll(ulong mpxpll);
|
||||
extern int set_px_corepll(ulong corepll);
|
||||
extern void read_from_px_regs(int set);
|
||||
extern void read_from_px_regs_altbank(int set);
|
||||
extern void set_altbank(void);
|
||||
extern void set_px_go(void);
|
||||
extern void set_px_go_with_watchdog(void);
|
||||
extern int disable_watchdog(cmd_tbl_t *cmdtp,
|
||||
int flag, int argc, char *argv[]);
|
||||
extern ulong strfractoint(uchar *strptr);
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright 2004 Freescale Semiconductor
|
||||
* Jeff Brown (jeffrey@freescale.com)
|
||||
* Copyright 2006 Freescale Semiconductor
|
||||
* Jeff Brown
|
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -32,29 +32,10 @@
|
|||
#include <ft_build.h>
|
||||
#endif
|
||||
|
||||
extern unsigned long get_board_sys_clk(ulong dummy);
|
||||
|
||||
|
||||
static __inline__ unsigned long get_dbat3u (void)
|
||||
{
|
||||
unsigned long dbat3u;
|
||||
asm volatile("mfspr %0, 542" : "=r" (dbat3u) :);
|
||||
return dbat3u;
|
||||
}
|
||||
|
||||
static __inline__ unsigned long get_dbat3l (void)
|
||||
{
|
||||
unsigned long dbat3l;
|
||||
asm volatile("mfspr %0, 543" : "=r" (dbat3l) :);
|
||||
return dbat3l;
|
||||
}
|
||||
|
||||
static __inline__ unsigned long get_msr (void)
|
||||
{
|
||||
unsigned long msr;
|
||||
asm volatile("mfmsr %0" : "=r" (msr) :);
|
||||
return msr;
|
||||
}
|
||||
#ifdef CONFIG_MPC8641HPCN
|
||||
extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
|
||||
int argc, char *argv[]);
|
||||
#endif
|
||||
|
||||
|
||||
int checkcpu (void)
|
||||
|
|
@ -74,8 +55,7 @@ int checkcpu (void)
|
|||
minor = PVR_MIN(pvr);
|
||||
|
||||
puts("CPU:\n");
|
||||
|
||||
printf(" Core: ");
|
||||
puts(" Core: ");
|
||||
|
||||
switch (ver) {
|
||||
case PVR_VER(PVR_86xx):
|
||||
|
|
@ -131,22 +111,19 @@ int checkcpu (void)
|
|||
printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
|
||||
}
|
||||
|
||||
printf(" L2: ");
|
||||
if (get_l2cr() & 0x80000000)
|
||||
printf("Enabled\n");
|
||||
else
|
||||
printf("Disabled\n");
|
||||
puts(" L2: ");
|
||||
if (get_l2cr() & 0x80000000)
|
||||
puts("Enabled\n");
|
||||
else
|
||||
puts("Disabled\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
static inline void
|
||||
soft_restart(unsigned long addr)
|
||||
{
|
||||
|
||||
#ifndef CONFIG_MPC8641HPCN
|
||||
|
||||
/* SRR0 has system reset vector, SRR1 has default MSR value */
|
||||
|
|
@ -158,301 +135,25 @@ soft_restart(unsigned long addr)
|
|||
__asm__ __volatile__ ("rfi");
|
||||
|
||||
#else /* CONFIG_MPC8641HPCN */
|
||||
out8(PIXIS_BASE+PIXIS_RST,0);
|
||||
|
||||
out8(PIXIS_BASE + PIXIS_RST, 0);
|
||||
|
||||
#endif /* !CONFIG_MPC8641HPCN */
|
||||
|
||||
while(1); /* not reached */
|
||||
}
|
||||
|
||||
|
||||
|
||||
#ifdef CONFIG_MPC8641HPCN
|
||||
|
||||
int set_px_sysclk(ulong sysclk)
|
||||
{
|
||||
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
|
||||
|
||||
/* Per table 27, page 58 of MPC8641HPCN spec*/
|
||||
switch(sysclk)
|
||||
{
|
||||
case 33:
|
||||
sysclk_s = 0x04;
|
||||
sysclk_r = 0x04;
|
||||
sysclk_v = 0x07;
|
||||
sysclk_aux = 0x00;
|
||||
break;
|
||||
case 40:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x20;
|
||||
sysclk_aux = 0x01;
|
||||
break;
|
||||
case 50:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x2A;
|
||||
sysclk_aux = 0x02;
|
||||
break;
|
||||
case 66:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x04;
|
||||
sysclk_v = 0x04;
|
||||
sysclk_aux = 0x03;
|
||||
break;
|
||||
case 83:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x4B;
|
||||
sysclk_aux = 0x04;
|
||||
break;
|
||||
case 100:
|
||||
sysclk_s = 0x01;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x5C;
|
||||
sysclk_aux = 0x05;
|
||||
break;
|
||||
case 134:
|
||||
sysclk_s = 0x06;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x3B;
|
||||
sysclk_aux = 0x06;
|
||||
break;
|
||||
case 166:
|
||||
sysclk_s = 0x06;
|
||||
sysclk_r = 0x1F;
|
||||
sysclk_v = 0x4B;
|
||||
sysclk_aux = 0x07;
|
||||
break;
|
||||
default:
|
||||
printf("Unsupported SYSCLK frequency.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
vclkh = (sysclk_s << 5) | sysclk_r ;
|
||||
vclkl = sysclk_v;
|
||||
out8(PIXIS_BASE+PIXIS_VCLKH,vclkh);
|
||||
out8(PIXIS_BASE+PIXIS_VCLKL,vclkl);
|
||||
|
||||
out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int set_px_mpxpll(ulong mpxpll)
|
||||
{
|
||||
u8 tmp;
|
||||
u8 val;
|
||||
switch(mpxpll)
|
||||
{
|
||||
case 2:
|
||||
case 4:
|
||||
case 6:
|
||||
case 8:
|
||||
case 10:
|
||||
case 12:
|
||||
case 14:
|
||||
case 16:
|
||||
val = (u8)mpxpll;
|
||||
break;
|
||||
default:
|
||||
printf("Unsupported MPXPLL ratio.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VSPEED1);
|
||||
tmp = (tmp & 0xF0) | (val & 0x0F);
|
||||
out8(PIXIS_BASE+PIXIS_VSPEED1,tmp);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int set_px_corepll(ulong corepll)
|
||||
{
|
||||
u8 tmp;
|
||||
u8 val;
|
||||
|
||||
switch ((int)corepll) {
|
||||
case 20:
|
||||
val = 0x08;
|
||||
break;
|
||||
case 25:
|
||||
val = 0x0C;
|
||||
break;
|
||||
case 30:
|
||||
val = 0x10;
|
||||
break;
|
||||
case 35:
|
||||
val = 0x1C;
|
||||
break;
|
||||
case 40:
|
||||
val = 0x14;
|
||||
break;
|
||||
case 45:
|
||||
val = 0x0E;
|
||||
break;
|
||||
default:
|
||||
printf("Unsupported COREPLL ratio.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VSPEED0);
|
||||
tmp = (tmp & 0xE0) | (val & 0x1F);
|
||||
out8(PIXIS_BASE+PIXIS_VSPEED0,tmp);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void read_from_px_regs(int set)
|
||||
{
|
||||
u8 tmp, mask = 0x1C;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCFGEN0);
|
||||
if (set)
|
||||
tmp = tmp | mask;
|
||||
else
|
||||
tmp = tmp & ~mask;
|
||||
out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp);
|
||||
}
|
||||
|
||||
void read_from_px_regs_altbank(int set)
|
||||
{
|
||||
u8 tmp, mask = 0x04;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCFGEN1);
|
||||
if (set)
|
||||
tmp = tmp | mask;
|
||||
else
|
||||
tmp = tmp & ~mask;
|
||||
out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp);
|
||||
}
|
||||
|
||||
void set_altbank(void)
|
||||
{
|
||||
u8 tmp;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VBOOT);
|
||||
tmp ^= 0x40;
|
||||
out8(PIXIS_BASE+PIXIS_VBOOT,tmp);
|
||||
}
|
||||
|
||||
|
||||
void set_px_go(void)
|
||||
{
|
||||
u8 tmp;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp & 0x1E;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp | 0x01;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
}
|
||||
|
||||
void set_px_go_with_watchdog(void)
|
||||
{
|
||||
u8 tmp;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp & 0x1E;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp | 0x09;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
}
|
||||
|
||||
int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
u8 tmp;
|
||||
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
tmp = tmp & 0x1E;
|
||||
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
|
||||
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
|
||||
tmp &= ~ 0x08; /* setting VCTL[WDEN] to 0 to disable watch dog */
|
||||
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
diswd, 1, 0, disable_watchdog,
|
||||
"diswd - Disable watchdog timer \n",
|
||||
NULL
|
||||
);
|
||||
|
||||
/* This function takes the non-integral cpu:mpx pll ratio
|
||||
* and converts it to an integer that can be used to assign
|
||||
* FPGA register values.
|
||||
* input: strptr i.e. argv[2]
|
||||
*/
|
||||
|
||||
ulong strfractoint(uchar *strptr)
|
||||
{
|
||||
int i,j,retval,intarr_len=0, decarr_len=0, mulconst, no_dec=0;
|
||||
ulong intval =0, decval=0;
|
||||
uchar intarr[3], decarr[3];
|
||||
|
||||
/* Assign the integer part to intarr[]
|
||||
* If there is no decimal point i.e.
|
||||
* if the ratio is an integral value
|
||||
* simply create the intarr.
|
||||
*/
|
||||
i=0;
|
||||
while(strptr[i] != 46)
|
||||
{
|
||||
if(strptr[i] == 0)
|
||||
{
|
||||
no_dec = 1;
|
||||
break; /* Break from loop once the end of string is reached */
|
||||
}
|
||||
|
||||
intarr[i] = strptr[i];
|
||||
i++;
|
||||
}
|
||||
|
||||
intarr_len = i; /* Assign length of integer part to intarr_len*/
|
||||
intarr[i] = '\0'; /* */
|
||||
|
||||
if(no_dec)
|
||||
{
|
||||
mulconst=10; /* Currently needed only for single digit corepll ratios */
|
||||
decval = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
j=0;
|
||||
i++; /* Skipping the decimal point */
|
||||
while ((strptr[i] > 47) && (strptr[i] < 58))
|
||||
{
|
||||
decarr[j] = strptr[i];
|
||||
i++;
|
||||
j++;
|
||||
}
|
||||
|
||||
decarr_len = j;
|
||||
decarr[j] = '\0';
|
||||
|
||||
mulconst=1;
|
||||
for(i=0; i<decarr_len;i++)
|
||||
mulconst = mulconst*10;
|
||||
decval = simple_strtoul(decarr,NULL,10);
|
||||
}
|
||||
|
||||
intval = simple_strtoul(intarr,NULL,10);
|
||||
intval = intval*mulconst;
|
||||
|
||||
retval = intval+decval;
|
||||
|
||||
return retval;
|
||||
|
||||
}
|
||||
|
||||
|
||||
#endif /* CONFIG_MPC8641HPCN */
|
||||
|
||||
|
||||
/* no generic way to do board reset. simply call soft_reset. */
|
||||
/*
|
||||
* No generic way to do board reset. Simply call soft_reset.
|
||||
*/
|
||||
void
|
||||
do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
char cmd;
|
||||
ulong addr, val;
|
||||
ulong corepll;
|
||||
#ifndef CONFIG_MPC8641HPCN
|
||||
|
||||
#ifdef CFG_RESET_ADDRESS
|
||||
addr = CFG_RESET_ADDRESS;
|
||||
ulong addr = CFG_RESET_ADDRESS;
|
||||
#else
|
||||
/*
|
||||
* note: when CFG_MONITOR_BASE points to a RAM address,
|
||||
|
|
@ -460,11 +161,9 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
* address. Better pick an address known to be invalid on your
|
||||
* system and assign it to CFG_RESET_ADDRESS.
|
||||
*/
|
||||
addr = CFG_MONITOR_BASE - sizeof (ulong);
|
||||
ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_MPC8641HPCN
|
||||
|
||||
/* flush and disable I/D cache */
|
||||
__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
|
||||
__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
|
||||
|
|
@ -478,90 +177,11 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
__asm__ __volatile__ ("isync");
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
soft_restart(addr);
|
||||
soft_restart(addr);
|
||||
|
||||
#else /* CONFIG_MPC8641HPCN */
|
||||
|
||||
if (argc > 1) {
|
||||
cmd = argv[1][1];
|
||||
switch(cmd) {
|
||||
case 'f': /* reset with frequency changed */
|
||||
if (argc < 5)
|
||||
goto my_usage;
|
||||
read_from_px_regs(0);
|
||||
|
||||
val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
|
||||
|
||||
corepll = strfractoint(argv[3]);
|
||||
val = val + set_px_corepll(corepll);
|
||||
val = val + set_px_mpxpll(simple_strtoul(argv[4],
|
||||
NULL, 10));
|
||||
if (val == 3) {
|
||||
printf("Setting registers VCFGEN0 and VCTL\n");
|
||||
read_from_px_regs(1);
|
||||
printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
|
||||
set_px_go();
|
||||
} else
|
||||
goto my_usage;
|
||||
|
||||
while (1); /* Not reached */
|
||||
|
||||
case 'l':
|
||||
if (argv[2][1] == 'f') {
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
/* reset with frequency changed */
|
||||
val = set_px_sysclk(simple_strtoul(argv[3],NULL,10));
|
||||
|
||||
corepll = strfractoint(argv[4]);
|
||||
val = val + set_px_corepll(corepll);
|
||||
val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
|
||||
if (val == 3) {
|
||||
printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs(1);
|
||||
read_from_px_regs_altbank(1);
|
||||
printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
|
||||
set_px_go_with_watchdog();
|
||||
} else
|
||||
goto my_usage;
|
||||
|
||||
while(1); /* Not reached */
|
||||
} else if(argv[2][1] == 'd'){
|
||||
/* Reset from next bank without changing frequencies but with watchdog timer enabled */
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
|
||||
set_px_go_with_watchdog();
|
||||
while(1); /* Not reached */
|
||||
} else {
|
||||
/* Reset from next bank without changing frequency and without watchdog timer enabled */
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
if(argc > 2)
|
||||
goto my_usage;
|
||||
printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
printf("Resetting board to boot from the other bank....\n");
|
||||
set_px_go();
|
||||
}
|
||||
|
||||
default:
|
||||
goto my_usage;
|
||||
}
|
||||
|
||||
my_usage:
|
||||
printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
|
||||
printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
|
||||
printf("For example: reset cf 40 2.5 10\n");
|
||||
printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
|
||||
return;
|
||||
} else
|
||||
out8(PIXIS_BASE+PIXIS_RST,0);
|
||||
mpc8641_reset_board(cmdtp, flag, argc, argv);
|
||||
|
||||
#endif /* !CONFIG_MPC8641HPCN */
|
||||
|
||||
|
|
@ -598,7 +218,6 @@ void dma_init(void)
|
|||
dma->satr0 = 0x00040000;
|
||||
dma->datr0 = 0x00040000;
|
||||
asm("sync; isync");
|
||||
return;
|
||||
}
|
||||
|
||||
uint dma_check(void)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue