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https://github.com/AsahiLinux/u-boot
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Merge branch 'mpc86xx'
This commit is contained in:
commit
eaa1fa16c4
2 changed files with 39 additions and 12 deletions
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@ -169,7 +169,7 @@ soft_restart(unsigned long addr)
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int set_px_sysclk(ulong sysclk)
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{
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u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux,tmp;
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u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
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/* Per table 27, page 58 of MPC8641HPCN spec*/
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switch(sysclk)
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@ -354,6 +354,24 @@ void set_px_go_with_watchdog(void)
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out8(PIXIS_BASE+PIXIS_VCTL,tmp);
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}
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int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE+PIXIS_VCTL);
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tmp = tmp & 0x1E;
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out8(PIXIS_BASE+PIXIS_VCTL,tmp);
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp &= ~ 0x08; /* setting VCTL[WDEN] to 0 to disable watch dog */
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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return 0;
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}
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U_BOOT_CMD(
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diswd, 1, 0, disable_watchdog,
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"diswd - Disable watchdog timer \n",
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NULL
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);
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/* This function takes the non-integral cpu:mpx pll ratio
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* and converts it to an integer that can be used to assign
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* FPGA register values.
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@ -509,18 +527,27 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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goto my_usage;
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while(1); /* Not reached */
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} else {
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/* Reset from next bank without changing frequencies */
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} else if(argv[2][1] == 'd'){
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/* Reset from next bank without changing frequencies but with watchdog timer enabled */
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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if(argc > 2)
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goto my_usage;
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printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
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set_px_go_with_watchdog();
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while(1); /* Not reached */
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} else {
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/* Reset from next bank without changing frequency and without watchdog timer enabled */
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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if(argc > 2)
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goto my_usage;
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printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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printf("Resetting board to boot from the other bank....\n");
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set_px_go();
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}
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default:
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@ -1088,24 +1088,24 @@ unsigned int enable_ddr(unsigned int ddr_num)
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* If the user wanted ECC (enabled via sdram_cfg[2])
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*/
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if (config == 0x02) {
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ddr->err_disable = 0x00000000;
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asm("sync;isync;");
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ddr->err_sbe = 0x00ff0000;
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ddr->err_int_en = 0x0000000d;
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sdram_cfg_1 |= 0x20000000; /* ECC_EN */
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}
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#endif
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/*
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* REV1 uses 1T timing.
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* REV2 may use 1T or 2T as configured by the user.
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* Set 1T or 2T timing based on 1 or 2 modules
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*/
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{
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uint pvr = get_pvr();
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if (pvr != PVR_85xx_REV1) {
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#if defined(CONFIG_DDR_2T_TIMING)
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if (!(no_dimm1 || no_dimm2)) {
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/*
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* 2T timing,because both DIMMS are present.
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* Enable 2T timing by setting sdram_cfg[16].
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*/
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sdram_cfg_1 |= 0x8000; /* 2T_EN */
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#endif
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}
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}
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