2016-04-07 14:00:11 +00:00
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CONFIG_ARM=y
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CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
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CONFIG_ARCH_ZYNQMP=y
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2017-02-10 12:57:35 +00:00
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CONFIG_SYS_TEXT_BASE=0x8000000
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2016-06-03 09:35:17 +00:00
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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2018-03-23 08:34:00 +00:00
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CONFIG_SPL=y
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2016-07-29 10:01:47 +00:00
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CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
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2016-04-07 14:00:11 +00:00
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CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
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2017-10-31 13:23:27 +00:00
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CONFIG_DEBUG_UART=y
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2016-11-29 14:14:57 +00:00
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CONFIG_DISTRO_DEFAULTS=y
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2016-04-07 14:00:11 +00:00
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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2016-05-17 06:38:53 +00:00
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CONFIG_SPL_LOAD_FIT=y
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2016-10-08 18:41:44 +00:00
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# CONFIG_DISPLAY_CPUINFO is not set
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2016-10-12 01:33:46 +00:00
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# CONFIG_DISPLAY_BOARDINFO is not set
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2018-03-28 12:38:15 +00:00
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CONFIG_BOARD_EARLY_INIT_R=y
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2016-10-06 05:55:15 +00:00
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CONFIG_SPL_OS_BOOT=y
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2017-12-08 14:01:19 +00:00
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CONFIG_SPL_RAM_SUPPORT=y
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CONFIG_SPL_RAM_DEVICE=y
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2018-03-12 16:18:38 +00:00
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CONFIG_SPL_ATF=y
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2016-04-07 14:00:11 +00:00
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CONFIG_SYS_PROMPT="ZynqMP> "
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CONFIG_CMD_MEMTEST=y
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2018-03-28 12:38:14 +00:00
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CONFIG_SYS_ALT_MEMTEST=y
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2017-12-01 14:35:43 +00:00
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CONFIG_CMD_CLK=y
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2016-04-07 14:00:11 +00:00
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# CONFIG_CMD_FLASH is not set
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2017-12-08 14:03:26 +00:00
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CONFIG_CMD_FPGA_LOADBP=y
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CONFIG_CMD_FPGA_LOADP=y
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2016-04-13 06:49:03 +00:00
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CONFIG_CMD_I2C=y
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2017-08-14 23:58:53 +00:00
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CONFIG_CMD_MMC=y
|
2016-04-07 14:00:11 +00:00
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CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_TIMER=y
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2016-04-24 21:29:26 +00:00
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CONFIG_CMD_EXT4_WRITE=y
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2016-07-15 06:41:46 +00:00
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CONFIG_SPL_OF_CONTROL=y
|
2016-04-07 14:00:11 +00:00
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CONFIG_OF_EMBED=y
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2017-08-28 11:16:32 +00:00
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|
CONFIG_ENV_IS_IN_FAT=y
|
2018-03-28 12:30:35 +00:00
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CONFIG_NET_RANDOM_ETHADDR=y
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2016-07-27 13:08:03 +00:00
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CONFIG_SPL_DM=y
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2016-07-15 06:41:46 +00:00
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CONFIG_SPL_DM_SEQ_ALIAS=y
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2017-12-08 13:50:42 +00:00
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CONFIG_CLK_ZYNQMP=y
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2016-01-13 10:55:37 +00:00
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CONFIG_FPGA_XILINX=y
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|
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CONFIG_FPGA_ZYNQMPPL=y
|
2016-09-08 20:11:59 +00:00
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|
|
CONFIG_DM_GPIO=y
|
2016-07-27 13:08:03 +00:00
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|
|
CONFIG_DM_I2C=y
|
2016-04-13 06:49:03 +00:00
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|
|
CONFIG_SYS_I2C_CADENCE=y
|
2017-12-08 13:46:30 +00:00
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|
|
CONFIG_MISC=y
|
2016-04-07 14:00:11 +00:00
|
|
|
CONFIG_DM_MMC=y
|
2016-12-07 13:10:28 +00:00
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|
|
CONFIG_MMC_SDHCI=y
|
2017-02-10 12:57:35 +00:00
|
|
|
CONFIG_MMC_SDHCI_ZYNQ=y
|
2018-03-28 12:17:19 +00:00
|
|
|
CONFIG_PHY_MARVELL=y
|
|
|
|
CONFIG_PHY_NATSEMI=y
|
|
|
|
CONFIG_PHY_REALTEK=y
|
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|
|
CONFIG_PHY_TI=y
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|
|
CONFIG_PHY_VITESSE=y
|
|
|
|
CONFIG_PHY_FIXED=y
|
2016-04-07 14:00:11 +00:00
|
|
|
CONFIG_DM_ETH=y
|
2018-01-31 08:18:33 +00:00
|
|
|
CONFIG_PHY_GIGE=y
|
|
|
|
CONFIG_ZYNQ_GEM=y
|
2017-10-31 13:23:27 +00:00
|
|
|
CONFIG_DEBUG_UART_ZYNQ=y
|
|
|
|
CONFIG_DEBUG_UART_BASE=0xff000000
|
|
|
|
CONFIG_DEBUG_UART_CLOCK=100000000
|
|
|
|
CONFIG_DEBUG_UART_ANNOUNCE=y
|
2017-11-06 08:16:05 +00:00
|
|
|
CONFIG_ZYNQ_SERIAL=y
|
2016-05-11 16:25:49 +00:00
|
|
|
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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