mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
arm64: zynqmp: Convert board to use zynqmp-clk driver
Use zynqmp clock driver instead of fixed clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek
parent
b0af10443a
commit
ee4983f73a
13 changed files with 302 additions and 5 deletions
290
arch/arm/dts/zynqmp-clk-ccf.dtsi
Normal file
290
arch/arm/dts/zynqmp-clk-ccf.dtsi
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@ -0,0 +1,290 @@
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/*
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* Clock specification for Xilinx ZynqMP
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*
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* (C) Copyright 2017, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/ {
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fclk0: fclk0 {
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status = "disabled";
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compatible = "xlnx,fclk";
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clocks = <&clkc 71>;
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};
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fclk1: fclk1 {
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status = "disabled";
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compatible = "xlnx,fclk";
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clocks = <&clkc 72>;
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};
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fclk2: fclk2 {
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status = "disabled";
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compatible = "xlnx,fclk";
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clocks = <&clkc 73>;
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};
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fclk3: fclk3 {
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status = "disabled";
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compatible = "xlnx,fclk";
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clocks = <&clkc 74>;
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};
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pss_ref_clk: pss_ref_clk {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <33333333>;
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};
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video_clk: video_clk {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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pss_alt_ref_clk: pss_alt_ref_clk {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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gt_crx_ref_clk: gt_crx_ref_clk {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <108000000>;
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};
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aux_ref_clk: aux_ref_clk {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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clkc: clkc {
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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compatible = "xlnx,zynqmp-clkc";
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clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
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clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
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clock-output-names = "iopll", "rpll", "apll", "dpll",
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"vpll", "iopll_to_fpd", "rpll_to_fpd",
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"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
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"acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
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"dbg_trace", "dbg_tstmp", "dp_video_ref",
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"dp_audio_ref", "dp_stc_ref", "gdma_ref",
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"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
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"gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
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"topsw_main", "topsw_lsbus", "gtgref0_ref",
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"lpd_switch", "lpd_lsbus", "usb0_bus_ref",
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"usb1_bus_ref", "usb3_dual_ref", "usb0",
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"usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
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"csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
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"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
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"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
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"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
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"uart0_ref", "uart1_ref", "spi0_ref",
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"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
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"can0_ref", "can1_ref", "can0", "can1",
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"dll_ref", "adma_ref", "timestamp_ref",
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"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
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};
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dp_aclk: dp_aclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-accuracy = <100>;
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};
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};
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&can0 {
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clocks = <&clkc 63>, <&clkc 31>;
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};
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&can1 {
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clocks = <&clkc 64>, <&clkc 31>;
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};
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&cpu0 {
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clocks = <&clkc 10>;
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};
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&fpd_dma_chan1 {
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clocks = <&clkc 19>, <&clkc 31>;
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};
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&fpd_dma_chan2 {
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clocks = <&clkc 19>, <&clkc 31>;
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};
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&fpd_dma_chan3 {
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clocks = <&clkc 19>, <&clkc 31>;
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};
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&fpd_dma_chan4 {
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clocks = <&clkc 19>, <&clkc 31>;
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};
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&fpd_dma_chan5 {
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clocks = <&clkc 19>, <&clkc 31>;
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};
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&fpd_dma_chan6 {
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clocks = <&clkc 19>, <&clkc 31>;
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};
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&fpd_dma_chan7 {
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clocks = <&clkc 19>, <&clkc 31>;
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};
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&fpd_dma_chan8 {
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clocks = <&clkc 19>, <&clkc 31>;
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};
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&gpu {
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clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;
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};
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&lpd_dma_chan1 {
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clocks = <&clkc 68>, <&clkc 31>;
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};
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&lpd_dma_chan2 {
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clocks = <&clkc 68>, <&clkc 31>;
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};
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&lpd_dma_chan3 {
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clocks = <&clkc 68>, <&clkc 31>;
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};
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&lpd_dma_chan4 {
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clocks = <&clkc 68>, <&clkc 31>;
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};
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&lpd_dma_chan5 {
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clocks = <&clkc 68>, <&clkc 31>;
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};
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&lpd_dma_chan6 {
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clocks = <&clkc 68>, <&clkc 31>;
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};
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&lpd_dma_chan7 {
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clocks = <&clkc 68>, <&clkc 31>;
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};
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&lpd_dma_chan8 {
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clocks = <&clkc 68>, <&clkc 31>;
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};
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&nand0 {
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clocks = <&clkc 60>, <&clkc 31>;
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};
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&gem0 {
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clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gem1 {
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clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gem2 {
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clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gem3 {
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clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gpio {
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clocks = <&clkc 31>;
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};
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&i2c0 {
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clocks = <&clkc 61>;
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};
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&i2c1 {
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clocks = <&clkc 62>;
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};
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&pcie {
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clocks = <&clkc 23>;
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};
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&qspi {
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clocks = <&clkc 53>, <&clkc 31>;
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};
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&sata {
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clocks = <&clkc 22>;
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};
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&sdhci0 {
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clocks = <&clkc 54>, <&clkc 31>;
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};
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&sdhci1 {
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clocks = <&clkc 55>, <&clkc 31>;
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};
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&spi0 {
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clocks = <&clkc 58>, <&clkc 31>;
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};
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&spi1 {
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clocks = <&clkc 59>, <&clkc 31>;
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};
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&uart0 {
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clocks = <&clkc 56>, <&clkc 31>;
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};
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&uart1 {
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clocks = <&clkc 57>, <&clkc 31>;
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};
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&usb0 {
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clocks = <&clkc 32>, <&clkc 34>;
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};
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&usb1 {
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clocks = <&clkc 33>, <&clkc 34>;
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};
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&watchdog0 {
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clocks = <&clkc 75>;
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};
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&xilinx_ams {
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clocks = <&clkc 70>;
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};
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&xilinx_drm {
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clocks = <&clkc 16>;
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};
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&xlnx_dp {
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clocks = <&dp_aclk>, <&clkc 17>;
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};
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&xlnx_dpdma {
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clocks = <&clkc 20>;
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};
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&xlnx_dp_snd_codec0 {
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clocks = <&clkc 17>;
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};
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@ -11,7 +11,7 @@
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "ZynqMP zc1751-xm015-dc1 RevA";
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@ -11,7 +11,7 @@
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "ZynqMP zc1751-xm016-dc2 RevA";
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@ -11,7 +11,7 @@
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "ZynqMP zc1751-xm018-dc4";
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@ -12,7 +12,7 @@
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "ZynqMP zc1751-xm019-dc5 RevA";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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@ -11,7 +11,7 @@
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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#include <dt-bindings/phy/phy.h>
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@ -45,6 +45,7 @@ CONFIG_ENV_IS_IN_FAT=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_CLK_ZYNQMP=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
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@ -44,6 +44,7 @@ CONFIG_OF_EMBED=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_CLK_ZYNQMP=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
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@ -34,6 +34,7 @@ CONFIG_ENV_IS_IN_FAT=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_CLK_ZYNQMP=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
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CONFIG_DM_GPIO=y
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@ -34,6 +34,7 @@ CONFIG_OF_EMBED=y
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CONFIG_ENV_IS_IN_FAT=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_CLK_ZYNQMP=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
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CONFIG_DM_GPIO=y
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@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SCSI_AHCI=y
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CONFIG_SATA_CEVA=y
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CONFIG_CLK_ZYNQMP=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
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@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SCSI_AHCI=y
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CONFIG_SATA_CEVA=y
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CONFIG_CLK_ZYNQMP=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
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@ -48,6 +48,7 @@ CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SCSI_AHCI=y
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CONFIG_SATA_CEVA=y
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CONFIG_CLK_ZYNQMP=y
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CONFIG_DFU_RAM=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQMPPL=y
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