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u-boot/arch/x86/cpu/ivybridge/Kconfig

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
# SPDX-License-Identifier: GPL-2.0
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:07 +00:00
#
# From Coreboot src/northbridge/intel/sandybridge/Kconfig
#
# Copyright (C) 2010 Google Inc.
#
config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
x86: Move common MRC Kconfig options to the common file At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-12 05:07:08 +00:00
select CACHE_MRC_BIN if HAVE_MRC
x86: kconfig: Imply HAVE_INTEL_ME in the platform Kconfig Intel Management Engine is required by the platform, however it's not a must have when building a U-Boot image. For example, during development normally programming ME firmware is a one-time effort. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-30 13:23:10 +00:00
imply HAVE_INTEL_ME
x86: kconfig: Imply ENABLE_MRC_CACHE in the platform Kconfig Platform knows whether MRC cache is implemented, but using it can be a choice of a specific board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-30 13:23:14 +00:00
imply ENABLE_MRC_CACHE
x86: Switch all boards to use DM SCSI After MMC is converted to DM, convert to use DM SCSI as well for all x86 boards and imply BLK for both MMC and SCSI drivers. CONFIG_SCSI_DEV_LIST is no longer used. Clean them up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-31 02:24:02 +00:00
imply AHCI_PCI
x86: ivybridge: kconfig: Imply platform specific drivers Imply drivers that are working with Ivybridge platform in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-30 13:23:18 +00:00
imply ICH_SPI
x86: Convert INTEL_ICH6_GPIO to Kconfig This converts Intel ICH6 GPIO driver to Kconfig, and add it to the imply list of platform drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-30 13:23:28 +00:00
imply INTEL_ICH6_GPIO
x86: Conditionally build the pinctrl_ich6 driver The pinctrl_ich6 driver is currently unconditionally built for all x86 boards. Let's use a Kconfig option to control the build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-10 13:25:01 +00:00
imply PINCTRL_ICH6
x86: ivybridge: kconfig: Imply platform specific drivers Imply drivers that are working with Ivybridge platform in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-30 13:23:18 +00:00
imply SCSI
ata: Migrate CONFIG_SCSI_AHCI to Kconfig And use 'imply' liberally. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-12-08 13:36:19 +00:00
imply SCSI_AHCI
x86: ivybridge: kconfig: Imply platform specific drivers Imply drivers that are working with Ivybridge platform in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-30 13:23:18 +00:00
imply SPI_FLASH
x86: kconfig: Move USB to platform Kconfig Like other peripheral drivers, move USB related drivers to platform Kconfig as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-30 13:23:27 +00:00
imply USB
imply USB_EHCI_HCD
x86: ivybridge: Imply USB_XHCI_HCD The Panther Point chipset connected to Ivybridge has xHC integrated, imply it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-04 02:04:15 +00:00
imply USB_XHCI_HCD
x86: ivybridge: kconfig: Imply platform specific drivers Imply drivers that are working with Ivybridge platform in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-30 13:23:18 +00:00
imply VIDEO_VESA
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:07 +00:00
if NORTHBRIDGE_INTEL_IVYBRIDGE
config DCACHE_RAM_BASE
default 0xff7e0000
config DCACHE_RAM_SIZE
default 0x20000
config DCACHE_RAM_MRC_VAR_SIZE
default 0x4000
config CPU_SPECIFIC_OPTIONS
def_bool y
select SMM_TSEG
x86: ivybridge: Implement SDRAM init Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:28 +00:00
select X86_RAMTEST
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:07 +00:00
config SMM_TSEG_SIZE
hex
default 0x800000
config ENABLE_VMX
bool "Enable VMX for virtualization"
default n
help
Virtual Machine Extensions are provided in many x86 CPUs. These
provide various facilities for allowing a host OS to provide an
environment where potentially several guest OSes have only
limited access to the underlying hardware. This is achieved
without resorting to software trapping and/or instruction set
emulation (which would be very slow).
Intel's implementation of this is called VT-x. This option enables
VT-x this so that the OS that is booted by U-Boot can make use of
these facilities. If this option is not enabled, then the host OS
will be unable to support virtualisation, or it will run very
slowly.
x86: ivybridge: Add FSP support IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:21 +00:00
config FSP_ADDR
hex
default 0xfff80000
config FSP_USE_UPD
bool
default n
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:25 +00:00
config FSP_BROKEN_HOB
bool
default y
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-13 05:42:07 +00:00
endif
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