2019-07-29 17:59:44 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* include/configs/condor.h
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* This file is Condor board configuration.
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*
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* Copyright (C) 2019 Renesas Electronics Corporation
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*/
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#ifndef __CONDOR_H
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#define __CONDOR_H
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#include "rcar-gen3-common.h"
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/* Environment compatibility */
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/* SH Ether */
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2022-12-04 15:13:52 +00:00
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#define CFG_SH_ETHER_USE_PORT 0
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2022-12-04 15:13:50 +00:00
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#define CFG_SH_ETHER_PHY_ADDR 0x1
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2022-12-04 15:13:51 +00:00
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#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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2022-12-04 15:13:49 +00:00
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#define CFG_SH_ETHER_CACHE_WRITEBACK
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2022-12-04 15:13:48 +00:00
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#define CFG_SH_ETHER_CACHE_INVALIDATE
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2022-12-04 15:13:47 +00:00
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#define CFG_SH_ETHER_ALIGNE_SIZE 64
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2019-07-29 17:59:44 +00:00
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/* Board Clock */
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/* XTAL_CLK : 33.33MHz */
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#endif /* __CONDOR_H */
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