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global: Migrate CONFIG_SH_ETHER_ALIGNE_SIZE to CFG

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Perform a simple rename of CONFIG_SH_ETHER_ALIGNE_SIZE to CFG_SH_ETHER_ALIGNE_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-04 10:13:47 -05:00
parent ddc4187033
commit 24513c3ac8
11 changed files with 19 additions and 19 deletions
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4
drivers/net/sh_eth.c
View file

@ -41,7 +41,7 @@
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
flush_dcache_range((unsigned long)addr, \
(unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
(unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE)))
#else
#define flush_cache_wback(...)
#endif
@ -49,7 +49,7 @@
#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
#define invalidate_cache(addr, len) \
{ \
unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \
unsigned long start, end; \
\
start = (unsigned long)addr; \

16
drivers/net/sh_eth.h
View file

@ -29,8 +29,8 @@
#endif /* defined(CONFIG_SH) */
/* base padding size is 16 */
#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
#ifndef CFG_SH_ETHER_ALIGNE_SIZE
#define CFG_SH_ETHER_ALIGNE_SIZE 16
#endif
/* Number of supported ports */
@ -47,7 +47,7 @@
/* The size of the tx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
#define TX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12)
/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
@ -62,9 +62,9 @@ struct tx_desc_s {
/* The size of the rx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
#define RX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12)
/* aligned cache line size */
#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
#define RX_BUF_ALIGNE_SIZE (CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
/* Rx descriptor. We always use 4 bytes of padding */
struct rx_desc_s {
@ -388,11 +388,11 @@ enum DMAC_M_BIT {
#endif
};
#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
#if CFG_SH_ETHER_ALIGNE_SIZE == 64
# define EMDR_DESC EDMR_DL1
#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
#elif CFG_SH_ETHER_ALIGNE_SIZE == 32
# define EMDR_DESC EDMR_DL0
#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
# define EMDR_DESC 0
#endif

2
include/configs/alt.h
View file

@ -26,7 +26,7 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */

2
include/configs/condor.h
View file

@ -19,7 +19,7 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */
/* XTAL_CLK : 33.33MHz */

2
include/configs/gose.h
View file

@ -25,7 +25,7 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */

2
include/configs/grpeach.h
View file

@ -22,6 +22,6 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_ALIGNE_SIZE 64
#endif /* __GRPEACH_H */

2
include/configs/koelsch.h
View file

@ -25,7 +25,7 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */

2
include/configs/lager.h
View file

@ -26,7 +26,7 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */

2
include/configs/porter.h
View file

@ -27,7 +27,7 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */

2
include/configs/silk.h
View file

@ -27,7 +27,7 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */

2
include/configs/stout.h
View file

@ -31,7 +31,7 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */