u-boot/arch/x86/cpu/intel_common/Makefile

# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2016 Google, Inc

ifdef CONFIG_HAVE_MRC
obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
endif

ifdef CONFIG_INTEL_CAR_CQOS
obj-$(CONFIG_TPL_BUILD) += car2.o
ifndef CONFIG_SPL_BUILD
obj-y += car2_uninit.o
endif
endif

obj-y += cpu.o
obj-y += fast_spi.o
obj-y += lpc.o
ifndef CONFIG_TARGET_EFI_APP
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
ifndef CONFIG_$(SPL_)X86_64
obj-y += microcode.o
endif
endif
obj-y += pch.o

ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
obj-y += cpu_from_spl.o
endif
endif
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`# SPDX-License-Identifier: GPL-2.0+`
x86: Move cache-as-RAM code into a common location This cache-as-RAM (CAR) code is common to several Intel chips. Create a new intel_common directory and move it in there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:06:53 +00:00			`#`
			`# Copyright (c) 2016 Google, Inc`

x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2017-01-16 14:03:46 +00:00			`ifdef CONFIG_HAVE_MRC`
x86: Allow 16-bit init to be in TPL At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-04-26 03:58:53 +00:00			`obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o`
x86: Support TPL in Intel common code Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-04-26 03:59:05 +00:00			`obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o`
			`obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o`
			`obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o`
x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2017-01-16 14:03:46 +00:00			`endif`
x86: Add support for newer CAR schemes Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-12-07 04:42:25 +00:00
			`ifdef CONFIG_INTEL_CAR_CQOS`
			`obj-$(CONFIG_TPL_BUILD) += car2.o`
			`ifndef CONFIG_SPL_BUILD`
			`obj-y += car2_uninit.o`
			`endif`
			`endif`

x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:06:58 +00:00			`obj-y += cpu.o`
x86: spi: Add helper functions for Intel Fast SPI Most x86 CPUs use a mechanism where the SPI flash is mapped into the very top of 32-bit address space, so that it can be executed in place and read simply by copying from memory. For an 8MB ROM the mapping starts at 0xff800000. However some recent Intel CPUs do not use a simple 1:1 memory map. Instead the map starts at a different address and not all of the SPI flash is accessible through the map. This 'Fast SPI' feature requires that U-Boot check the location of the map. It is also possible (optionally) to read from the SPI flash using a driver. Add support for booting from Fast SPI. The memory-mapped version is used by both TPL and SPL on Apollo Lake. In respect of a SPI flash driver, the actual SPI driver is ich.c - this just adds a few helper functions and definitions. This is used by Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-12-07 04:41:43 +00:00			`obj-y += fast_spi.o`
x86: Move common LPC code to its own place Some of the LPC code is common to several Intel LPC devices. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:06:57 +00:00			`obj-y += lpc.o`
x86: Rename efi-x86 target to efi-x86_app To avoid confusion, let's rename the efi-x86 target to efi-x86_app. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 2018-06-12 15:36:24 +00:00			`ifndef CONFIG_TARGET_EFI_APP`
x86: Support TPL in Intel common code Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-04-26 03:59:05 +00:00			`obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o`
			`ifndef CONFIG_$(SPL_)X86_64`
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:06:54 +00:00			`obj-y += microcode.o`
			`endif`
x86: Support TPL in Intel common code Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-04-26 03:59:05 +00:00			`endif`
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-16 13:44:36 +00:00			`obj-y += pch.o`
x86: Add common Intel code for SPL Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-04-26 03:58:56 +00:00
			`ifdef CONFIG_SPL`
			`ifndef CONFIG_SPL_BUILD`
			`obj-y += cpu_from_spl.o`
			`endif`
			`endif`