u-boot/arch/x86/cpu/intel_common/Makefile

# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2016 Google, Inc

ifdef CONFIG_HAVE_MRC
obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += car.o
obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o
obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o
obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o
endif
obj-y += cpu.o
obj-y += lpc.o
ifndef CONFIG_TARGET_EFI
obj-y += microcode.o
endif
obj-y += pch.o
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`# SPDX-License-Identifier: GPL-2.0+`
x86: Move cache-as-RAM code into a common location This cache-as-RAM (CAR) code is common to several Intel chips. Create a new intel_common directory and move it in there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:06:53 +00:00			`#`
			`# Copyright (c) 2016 Google, Inc`

x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2017-01-16 14:03:46 +00:00			`ifdef CONFIG_HAVE_MRC`
			`obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += car.o`
			`obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o`
			`obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o`
			`obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o`
			`endif`
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:06:58 +00:00			`obj-y += cpu.o`
x86: Move common LPC code to its own place Some of the LPC code is common to several Intel LPC devices. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:06:57 +00:00			`obj-y += lpc.o`
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:06:54 +00:00			`ifndef CONFIG_TARGET_EFI`
			`obj-y += microcode.o`
			`endif`
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-16 13:44:36 +00:00			`obj-y += pch.o`