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u-boot/include/configs/grpeach.h

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ARM: dts: renesas: Add RZ/A1 GR-Peach board Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-23 19:53:59 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration settings for the Renesas GRPEACH board
*
* Copyright (C) 2017-2019 Renesas Electronics
*/
#ifndef __GRPEACH_H
#define __GRPEACH_H
/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
/* Miscellaneous */
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:37 +00:00
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
ARM: dts: renesas: Add RZ/A1 GR-Peach board Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-23 19:53:59 +00:00
/* Network interface */
global: Migrate CONFIG_SH_ETHER_USE_PORT to CFG Perform a simple rename of CONFIG_SH_ETHER_USE_PORT to CFG_SH_ETHER_USE_PORT Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:13:52 +00:00
#define CFG_SH_ETHER_USE_PORT 0
global: Migrate CONFIG_SH_ETHER_PHY_ADDR to CFG Perform a simple rename of CONFIG_SH_ETHER_PHY_ADDR to CFG_SH_ETHER_PHY_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:13:50 +00:00
#define CFG_SH_ETHER_PHY_ADDR 0
global: Migrate CONFIG_SH_ETHER_PHY_MODE to CFG Perform a simple rename of CONFIG_SH_ETHER_PHY_MODE to CFG_SH_ETHER_PHY_MODE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:13:51 +00:00
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
global: Migrate CONFIG_SH_ETHER_CACHE_WRITEBACK to CFG Perform a simple rename of CONFIG_SH_ETHER_CACHE_WRITEBACK to CFG_SH_ETHER_CACHE_WRITEBACK Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:13:49 +00:00
#define CFG_SH_ETHER_CACHE_WRITEBACK
global: Migrate CONFIG_SH_ETHER_CACHE_INVALIDATE to CFG Perform a simple rename of CONFIG_SH_ETHER_CACHE_INVALIDATE to CFG_SH_ETHER_CACHE_INVALIDATE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:13:48 +00:00
#define CFG_SH_ETHER_CACHE_INVALIDATE
global: Migrate CONFIG_SH_ETHER_ALIGNE_SIZE to CFG Perform a simple rename of CONFIG_SH_ETHER_ALIGNE_SIZE to CFG_SH_ETHER_ALIGNE_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-04 15:13:47 +00:00
#define CFG_SH_ETHER_ALIGNE_SIZE 64
ARM: dts: renesas: Add RZ/A1 GR-Peach board Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-08-23 19:53:59 +00:00
#endif /* __GRPEACH_H */
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