2011-10-14 02:58:24 +00:00
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/*
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* ddr_defs.h
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*
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* ddr specific header
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2011-10-14 02:58:24 +00:00
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*/
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#ifndef _DDR_DEFS_H
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#define _DDR_DEFS_H
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#include <asm/arch/hardware.h>
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2012-07-24 21:55:38 +00:00
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#include <asm/emif.h>
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2011-10-14 02:58:24 +00:00
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/* AM335X EMIF Register values */
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_START_EN (0x1)
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2013-12-10 09:32:22 +00:00
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#ifdef CONFIG_AM43XX
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#define DDR_CKE_CTRL_NORMAL 0x3
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#else
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2012-07-24 21:03:24 +00:00
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#define DDR_CKE_CTRL_NORMAL 0x1
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2013-12-10 09:32:22 +00:00
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#endif
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2013-03-14 21:11:16 +00:00
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#define PHY_EN_DYN_PWRDN (0x1 << 20)
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2011-10-14 02:58:24 +00:00
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2012-10-18 01:21:12 +00:00
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/* Micron MT47H128M16RT-25E */
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2012-10-18 01:21:13 +00:00
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#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
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#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
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#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
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#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
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#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
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#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
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#define MT47H128M16RT25E_RATIO 0x80
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#define MT47H128M16RT25E_RD_DQS 0x12
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#define MT47H128M16RT25E_PHY_WR_DATA 0x40
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#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
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#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
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2011-10-14 02:58:24 +00:00
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2012-07-30 21:49:50 +00:00
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/* Micron MT41J128M16JT-125 */
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2013-12-19 04:30:29 +00:00
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#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
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2012-10-18 01:21:13 +00:00
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#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
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#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
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#define MT41J128MJT125_EMIF_TIM3 0x501F830F
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#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
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#define MT41J128MJT125_EMIF_SDREF 0x0000093B
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#define MT41J128MJT125_ZQ_CFG 0x50074BE4
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#define MT41J128MJT125_RATIO 0x40
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#define MT41J128MJT125_INVERT_CLKOUT 0x1
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#define MT41J128MJT125_RD_DQS 0x3B
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#define MT41J128MJT125_WR_DQS 0x85
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#define MT41J128MJT125_PHY_WR_DATA 0xC1
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#define MT41J128MJT125_PHY_FIFO_WE 0x100
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#define MT41J128MJT125_IOCTRL_VALUE 0x18B
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2012-07-30 21:49:50 +00:00
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2016-05-16 06:17:24 +00:00
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/* Micron MT41J128M16JT-125 at 400MHz*/
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#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
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#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
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#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
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#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
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#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
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#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
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#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
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#define MT41J128MJT125_RATIO_400MHz 0x80
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#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
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#define MT41J128MJT125_RD_DQS_400MHz 0x3A
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#define MT41J128MJT125_WR_DQS_400MHz 0x3B
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#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
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#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
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2014-01-31 16:34:14 +00:00
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/* Micron MT41K128M16JT-187E */
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#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
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#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
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#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
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#define MT41K128MJT187E_EMIF_TIM3 0x501F830F
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#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
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#define MT41K128MJT187E_EMIF_SDREF 0x0000093B
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#define MT41K128MJT187E_ZQ_CFG 0x50074BE4
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#define MT41K128MJT187E_RATIO 0x40
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#define MT41K128MJT187E_INVERT_CLKOUT 0x1
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#define MT41K128MJT187E_RD_DQS 0x3B
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#define MT41K128MJT187E_WR_DQS 0x85
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#define MT41K128MJT187E_PHY_WR_DATA 0xC1
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#define MT41K128MJT187E_PHY_FIFO_WE 0x100
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#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
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2013-11-07 05:57:33 +00:00
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/* Micron MT41J64M16JT-125 */
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#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
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/* Micron MT41J256M16JT-125 */
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#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
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2013-01-11 00:53:31 +00:00
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/* Micron MT41J256M8HX-15E */
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2013-12-19 04:30:29 +00:00
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#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
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2013-01-11 00:53:31 +00:00
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#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
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#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
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#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
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#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
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#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
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#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
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#define MT41J256M8HX15E_RATIO 0x40
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#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
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#define MT41J256M8HX15E_RD_DQS 0x3B
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#define MT41J256M8HX15E_WR_DQS 0x85
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#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
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#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
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#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
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2013-03-21 04:30:02 +00:00
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/* Micron MT41K256M16HA-125E */
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2013-04-10 13:10:54 +00:00
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#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
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#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
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2013-04-12 16:38:16 +00:00
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#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
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#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
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#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
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2013-04-10 13:10:54 +00:00
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#define MT41K256M16HA125E_EMIF_SDREF 0xC30
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2013-03-21 04:30:02 +00:00
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#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
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2013-04-10 13:10:54 +00:00
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#define MT41K256M16HA125E_RATIO 0x80
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2013-03-21 04:30:02 +00:00
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#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
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2013-04-12 16:38:16 +00:00
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#define MT41K256M16HA125E_RD_DQS 0x38
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#define MT41K256M16HA125E_WR_DQS 0x44
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#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
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#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
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2013-03-21 04:30:02 +00:00
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#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
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2013-01-14 05:32:20 +00:00
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/* Micron MT41J512M8RH-125 on EVM v1.5 */
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2013-12-19 04:30:29 +00:00
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#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
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2013-01-14 05:32:20 +00:00
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#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
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#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
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#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
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#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
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#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
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#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
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#define MT41J512M8RH125_RATIO 0x80
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#define MT41J512M8RH125_INVERT_CLKOUT 0x0
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#define MT41J512M8RH125_RD_DQS 0x3B
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#define MT41J512M8RH125_WR_DQS 0x3C
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#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
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#define MT41J512M8RH125_PHY_WR_DATA 0x74
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#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
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2013-01-11 00:53:31 +00:00
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2013-04-04 22:27:57 +00:00
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/* Samsung K4B2G1646E-BIH9 */
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2013-12-19 04:30:29 +00:00
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#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
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2013-09-10 09:12:26 +00:00
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#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
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#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
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#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
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#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
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#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
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2013-04-04 22:27:57 +00:00
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#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
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2013-09-10 09:12:26 +00:00
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#define K4B2G1646EBIH9_RATIO 0x80
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#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
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#define K4B2G1646EBIH9_RD_DQS 0x35
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#define K4B2G1646EBIH9_WR_DQS 0x3A
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#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
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#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
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2013-04-04 22:27:57 +00:00
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#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
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2013-12-10 09:32:22 +00:00
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#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
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#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
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#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
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#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
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#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
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#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
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#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
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2013-12-10 09:32:23 +00:00
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#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
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#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
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#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
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#define DDR3_DATA0_IOCTRL_VALUE 0x84
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#define DDR3_DATA1_IOCTRL_VALUE 0x84
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#define DDR3_DATA2_IOCTRL_VALUE 0x84
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#define DDR3_DATA3_IOCTRL_VALUE 0x84
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2013-03-15 10:07:07 +00:00
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/**
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* Configure DMM
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*/
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void config_dmm(const struct dmm_lisa_map_regs *regs);
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2011-10-14 02:58:24 +00:00
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/**
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* Configure SDRAM
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*/
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2013-03-15 10:07:03 +00:00
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void config_sdram(const struct emif_regs *regs, int nr);
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2013-12-10 09:32:22 +00:00
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void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
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2011-10-14 02:58:24 +00:00
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/**
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* Set SDRAM timings
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*/
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2013-03-15 10:07:03 +00:00
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void set_sdram_timings(const struct emif_regs *regs, int nr);
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2011-10-14 02:58:24 +00:00
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/**
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* Configure DDR PHY
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*/
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2013-03-15 10:07:03 +00:00
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void config_ddr_phy(const struct emif_regs *regs, int nr);
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struct ddr_cmd_regs {
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unsigned int resv0[7];
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unsigned int cm0csratio; /* offset 0x01C */
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2013-11-07 16:42:57 +00:00
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unsigned int resv1[3];
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2013-03-15 10:07:03 +00:00
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unsigned int cm0iclkout; /* offset 0x02C */
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unsigned int resv2[8];
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unsigned int cm1csratio; /* offset 0x050 */
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2013-11-07 16:42:57 +00:00
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unsigned int resv3[3];
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2013-03-15 10:07:03 +00:00
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unsigned int cm1iclkout; /* offset 0x060 */
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unsigned int resv4[8];
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unsigned int cm2csratio; /* offset 0x084 */
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2013-11-07 16:42:57 +00:00
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unsigned int resv5[3];
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2013-03-15 10:07:03 +00:00
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unsigned int cm2iclkout; /* offset 0x094 */
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unsigned int resv6[3];
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};
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struct ddr_data_regs {
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unsigned int dt0rdsratio0; /* offset 0x0C8 */
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unsigned int resv1[4];
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unsigned int dt0wdsratio0; /* offset 0x0DC */
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unsigned int resv2[4];
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unsigned int dt0wiratio0; /* offset 0x0F0 */
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unsigned int resv3;
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unsigned int dt0wimode0; /* offset 0x0F8 */
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unsigned int dt0giratio0; /* offset 0x0FC */
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unsigned int resv4;
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unsigned int dt0gimode0; /* offset 0x104 */
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unsigned int dt0fwsratio0; /* offset 0x108 */
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unsigned int resv5[4];
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unsigned int dt0dqoffset; /* offset 0x11C */
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unsigned int dt0wrsratio0; /* offset 0x120 */
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unsigned int resv6[4];
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unsigned int dt0rdelays0; /* offset 0x134 */
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unsigned int dt0dldiff0; /* offset 0x138 */
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unsigned int resv7[12];
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};
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2011-10-14 02:58:24 +00:00
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/**
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* This structure represents the DDR registers on AM33XX devices.
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2012-07-30 18:49:47 +00:00
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* We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
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* correspond to DATA1 registers defined here.
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2011-10-14 02:58:24 +00:00
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*/
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struct ddr_regs {
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2013-07-02 10:05:59 +00:00
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unsigned int resv0[3];
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unsigned int cm0config; /* offset 0x00C */
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unsigned int cm0configclk; /* offset 0x010 */
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2012-07-30 18:49:47 +00:00
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unsigned int resv1[2];
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2013-07-02 10:05:59 +00:00
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unsigned int cm0csratio; /* offset 0x01C */
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2013-11-07 16:42:57 +00:00
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unsigned int resv2[3];
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2011-10-14 02:58:24 +00:00
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unsigned int cm0iclkout; /* offset 0x02C */
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2013-07-02 10:05:59 +00:00
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unsigned int resv3[4];
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unsigned int cm1config; /* offset 0x040 */
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unsigned int cm1configclk; /* offset 0x044 */
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unsigned int resv4[2];
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2011-10-14 02:58:24 +00:00
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unsigned int cm1csratio; /* offset 0x050 */
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2013-11-07 16:42:57 +00:00
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unsigned int resv5[3];
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2011-10-14 02:58:24 +00:00
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unsigned int cm1iclkout; /* offset 0x060 */
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2013-07-02 10:05:59 +00:00
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unsigned int resv6[4];
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unsigned int cm2config; /* offset 0x074 */
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unsigned int cm2configclk; /* offset 0x078 */
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unsigned int resv7[2];
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2011-10-14 02:58:24 +00:00
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unsigned int cm2csratio; /* offset 0x084 */
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2013-11-07 16:42:57 +00:00
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unsigned int resv8[3];
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2011-10-14 02:58:24 +00:00
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unsigned int cm2iclkout; /* offset 0x094 */
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2013-07-02 10:05:59 +00:00
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unsigned int resv9[12];
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2011-10-14 02:58:24 +00:00
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unsigned int dt0rdsratio0; /* offset 0x0C8 */
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2013-07-02 10:05:59 +00:00
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unsigned int resv10[4];
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2011-10-14 02:58:24 +00:00
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unsigned int dt0wdsratio0; /* offset 0x0DC */
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2013-07-02 10:05:59 +00:00
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unsigned int resv11[4];
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2011-10-14 02:58:24 +00:00
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unsigned int dt0wiratio0; /* offset 0x0F0 */
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2013-07-02 10:05:59 +00:00
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unsigned int resv12;
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2012-07-30 18:49:47 +00:00
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unsigned int dt0wimode0; /* offset 0x0F8 */
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2011-10-14 02:58:24 +00:00
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unsigned int dt0giratio0; /* offset 0x0FC */
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2013-07-02 10:05:59 +00:00
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unsigned int resv13;
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2012-07-30 18:49:47 +00:00
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unsigned int dt0gimode0; /* offset 0x104 */
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2011-10-14 02:58:24 +00:00
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unsigned int dt0fwsratio0; /* offset 0x108 */
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2013-07-02 10:05:59 +00:00
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unsigned int resv14[4];
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2012-07-30 18:49:47 +00:00
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unsigned int dt0dqoffset; /* offset 0x11C */
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2011-10-14 02:58:24 +00:00
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unsigned int dt0wrsratio0; /* offset 0x120 */
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2013-07-02 10:05:59 +00:00
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unsigned int resv15[4];
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2011-10-14 02:58:24 +00:00
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unsigned int dt0rdelays0; /* offset 0x134 */
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unsigned int dt0dldiff0; /* offset 0x138 */
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};
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/**
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* Encapsulates DDR CMD control registers.
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*/
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struct cmd_control {
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unsigned long cmd0csratio;
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unsigned long cmd0csforce;
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unsigned long cmd0csdelay;
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unsigned long cmd0iclkout;
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unsigned long cmd1csratio;
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unsigned long cmd1csforce;
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unsigned long cmd1csdelay;
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unsigned long cmd1iclkout;
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unsigned long cmd2csratio;
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unsigned long cmd2csforce;
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unsigned long cmd2csdelay;
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unsigned long cmd2iclkout;
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};
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/**
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* Encapsulates DDR DATA registers.
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*/
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struct ddr_data {
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unsigned long datardsratio0;
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unsigned long datawdsratio0;
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unsigned long datawiratio0;
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unsigned long datagiratio0;
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unsigned long datafwsratio0;
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unsigned long datawrsratio0;
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};
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/**
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* Configure DDR CMD control registers
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*/
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2013-03-15 10:07:03 +00:00
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void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
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2011-10-14 02:58:24 +00:00
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/**
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* Configure DDR DATA registers
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*/
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2013-03-15 10:07:03 +00:00
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void config_ddr_data(const struct ddr_data *data, int nr);
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2011-10-14 02:58:24 +00:00
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/**
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* This structure represents the DDR io control on AM33XX devices.
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*/
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struct ddr_cmdtctrl {
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unsigned int cm0ioctl;
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unsigned int cm1ioctl;
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unsigned int cm2ioctl;
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unsigned int resv2[12];
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unsigned int dt0ioctl;
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unsigned int dt1ioctl;
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2013-12-10 09:32:22 +00:00
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unsigned int dt2ioctrl;
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unsigned int dt3ioctrl;
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unsigned int resv3[4];
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unsigned int emif_sdram_config_ext;
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};
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struct ctrl_ioregs {
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unsigned int cm0ioctl;
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unsigned int cm1ioctl;
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unsigned int cm2ioctl;
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unsigned int dt0ioctl;
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unsigned int dt1ioctl;
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unsigned int dt2ioctrl;
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unsigned int dt3ioctrl;
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unsigned int emif_sdram_config_ext;
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2011-10-14 02:58:24 +00:00
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};
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/**
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* Configure DDR io control registers
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*/
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2013-12-10 09:32:22 +00:00
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void config_io_ctrl(const struct ctrl_ioregs *ioregs);
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2011-10-14 02:58:24 +00:00
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struct ddr_ctrl {
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unsigned int ddrioctrl;
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unsigned int resv1[325];
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unsigned int ddrckectrl;
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};
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2013-12-10 09:32:22 +00:00
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void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
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2012-10-18 01:21:12 +00:00
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const struct ddr_data *data, const struct cmd_control *ctrl,
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2013-03-15 10:07:03 +00:00
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const struct emif_regs *regs, int nr);
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2013-12-10 09:32:22 +00:00
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void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
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2011-10-14 02:58:24 +00:00
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#endif /* _DDR_DEFS_H */
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