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u-boot/drivers/clk/Kconfig

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clk: move Kconfig options into sub-menu Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-12 07:36:38 +00:00
menu "Clock"
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
config CLK
bool "Enable clock driver support"
depends on DM
help
This allows drivers to be provided for clock generators, including
oscillators and PLLs. Devices can use a common clock API to request
a particular clock rate and check on available clocks. Clocks can
feed into other clocks in a tree structure, with multiplexers to
choose the source for each clock.
clk: rename CONFIG_SPL_CLK_SUPPORT to CONFIG_SPL_CLK Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-11 22:31:46 +00:00
config SPL_CLK
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
bool "Enable clock support in SPL"
clk: Kconfig: Add dependences of SPL_CLK The SPL_CLK config should depend on SPL && SPL_DM. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-31 07:21:57 +00:00
depends on CLK && SPL && SPL_DM
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
help
The clock subsystem adds a small amount of overhead to the image.
If this is acceptable and you have a need to use clock drivers in
SPL, enable this option. It might provide a cleaner interface to
setting up clocks within SPL, and allows the same drivers to be
used as U-Boot proper.
clk: move Kconfig options into sub-menu Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-12 07:36:38 +00:00
spl: dm: Kconfig: split CLK support for SPL and TPL Introduce TPL_CLK to allow finer-grained selection of TPL features for feature-rich (i.e. DM-based) TPL stages. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-28 23:45:01 +00:00
config TPL_CLK
bool "Enable clock support in TPL"
depends on CLK && TPL_DM
help
The clock subsystem adds a small amount of overhead to the image.
If this is acceptable and you have a need to use clock drivers in
SPL, enable this option. It might provide a cleaner interface to
setting up clocks within TPL, and allows the same drivers to be
used as U-Boot proper.
dm: clk: add BCM6345 clock driver This is a simplified version of linux/arch/mips/bcm63xx/clk.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-07 18:13:01 +00:00
config CLK_BCM6345
bool "Clock controller driver for BCM6345"
depends on CLK && ARCH_BMIPS
default y
help
This clock driver adds support for enabling and disabling peripheral
clocks on BCM6345 SoCs. HW has no rate changing capabilities.
clk: boston: Providea simple driver for Boston board clocks Add a simple driver for the clocks provided by the MIPS Boston development board. The system provides information about 2 clocks whose rates are fixed by the bitfile flashed in the boards FPGA, and this driver simply reads the rates of these 2 clocks. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-08 06:47:38 +00:00
config CLK_BOSTON
def_bool y if TARGET_BOSTON
depends on CLK
select REGMAP
select SYSCON
help
Enable this to support the clocks
clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs rename it to a more generic clk_stm32f.c Fix also some checkpatch errors/warnings. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-15 12:14:48 +00:00
config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
default y
help
This clock driver adds support for RCC clock management
for STM32F4 and STM32F7 SoCs.
clk: Introduce TI System Control Interface (TI SCI) clock driver Some TI Keystone 2 and K3 family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and the Device Management and Security Controller on AM65x SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a clock driver that communicates to the system controller over the TI SCI protocol for performing clock management of various devices present on the SoC. Various clock functionality is achieved by the means of different TI SCI device operations provided by the TI SCI framework. This code is loosely based on the drivers/clk/keystone/sci-clk.c driver of the Linux kernel. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:43 +00:00
config CLK_TI_SCI
bool "TI System Control Interface (TI SCI) clock driver"
depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL
help
This enables the clock driver support over TI System Control Interface
available on some new TI's SoCs. If you wish to use clock resources
managed by the TI System Controller, say Y here. Otherwise, say N.
ARC: clk: introduce HSDK CGU clock driver Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-10 18:20:08 +00:00
config CLK_HSDK
bool "Enable cgu clock driver for HSDK"
depends on CLK
help
Enable this to support the cgu clocks on Synopsys ARC HSDK
clk: Add support for Arm's Versatile Express OSC clock generators The Arm Versatile Express and Juno development boards contain an OSC clock generator that can be accessed through the Versatile Express config bus. The generators are quite often being controlled by some MCU and the config bus offers a uniform way of exposing them. Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-09-17 16:50:00 +00:00
config CLK_VEXPRESS_OSC
bool "Enable driver for Arm Versatile Express OSC clock generators"
depends on CLK && VEXPRESS_CONFIG
help
This clock driver adds support for clock generators present on
Arm Versatile Express platforms.
clk: zynq: Add zynq clock framework driver Add a clock framework driver for the zynq platform. The driver is based on the platform zynq clock driver but reworked to use static functions instead of run-time generated objects even for unused clocks. Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the ps-clk-frequency from the device tree. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-17 15:27:29 +00:00
config CLK_ZYNQ
bool "Enable clock driver support for Zynq"
depends on CLK && ARCH_ZYNQ
default y
help
This clock driver adds support for clock realted settings for
Zynq platform.
clk: zynqmp: Add clock driver support for zynqmp Add basic clock driver support for zynqmp which sets the required clock for GEM controller Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-11-15 10:45:41 +00:00
config CLK_ZYNQMP
bool "Enable clock driver support for ZynqMP"
depends on ARCH_ZYNQMP
help
This clock driver adds support for clock realted settings for
ZynqMP platform.
clk: add driver for stm32mp1 add RCC clock driver for STMP32MP157 - base on driver model = UCLASS_CLK - support ops to enable, disable and get rate of all SOC clock needed by U-Boot Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-12 09:46:15 +00:00
config CLK_STM32MP1
bool "Enable RCC clock driver for STM32MP1"
depends on ARCH_STM32MP && CLK
default y
help
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP1's on-SoC clocks.
clk: sifive: Factor-out PLL library as separate module To match SiFive clock driver with latest Linux, we factor-out PLL library as separate module under drivers/clk/analogbits. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-25 06:31:02 +00:00
source "drivers/clk/analogbits/Kconfig"
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
source "drivers/clk/at91/Kconfig"
clk: Kconfig: Ascending order to sub directiory kconfigs sourcing of sub directiory kconfig files are not in proper order, so keep them in ascending order. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 12:56:18 +00:00
source "drivers/clk/exynos/Kconfig"
clk: imx: add clk driver for i.MX8QXP Add clk driver for i.MX8QXP. This basic version supports clk enable/disable/get_rate/set_rate operations for I2C, ENET, SDHC0 and UART clocks. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-18 12:28:30 +00:00
source "drivers/clk/imx/Kconfig"
clk: create meson directory and move related drivers In order to support the Amlogic G12A clock controller, re-architect the clock files into a meson directory. No functionnal changes. MAINTAINERS entry is also updated. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-02-10 13:54:30 +00:00
source "drivers/clk/meson/Kconfig"
driver: clk: Add support for clocks on Armada 37xx The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-04-24 15:21:25 +00:00
source "drivers/clk/mvebu/Kconfig"
clk: Add Actions Semi OWL clock support This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-14 18:08:35 +00:00
source "drivers/clk/owl/Kconfig"
clk: Kconfig: Ascending order to sub directiory kconfigs sourcing of sub directiory kconfig files are not in proper order, so keep them in ascending order. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 12:56:18 +00:00
source "drivers/clk/renesas/Kconfig"
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
source "drivers/clk/sunxi/Kconfig"
clk: Add SiFive FU540 PRCI clock driver Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-25 08:14:49 +00:00
source "drivers/clk/sifive/Kconfig"
clk: Kconfig: Ascending order to sub directiory kconfigs sourcing of sub directiory kconfig files are not in proper order, so keep them in ascending order. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 12:56:18 +00:00
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
clk: uniphier: add Media I/O clock driver for UniPhier SoCs This is the initial commit for the UniPhier clock drivers. Currently, only the Media I/O clock is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-02 12:11:32 +00:00
clk: Add ICS8N3QV01 driver Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-04-27 12:53:15 +00:00
config ICS8N3QV01
bool "Enable ICS8N3QV01 VCXO driver"
depends on CLK
help
Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
Crystal Oscillator). The output frequency can be programmed via an
I2C interface.
clk: Add MPC83xx clock driver Add a clock driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:36 +00:00
config CLK_MPC83XX
bool "Enable MPC83xx clock driver"
depends on CLK
help
Support for the clock driver of the MPC83xx series of SoCs.
clk: move Kconfig options into sub-menu Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-01-12 07:36:38 +00:00
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